For the most recent list of errata for the Nios® II EDS, search the Knowledge Base under Support on the Altera website. You can use the Knowledge Base to search for errata based on the product version affected and other criteria.
For more information about Nios II EDS features, refer to the Nios II handbooks.
The v15.0 Nios II EDS includes the following new and enhanced features:
- New MAX 10 analog-to-digital converter (ADC) HAL driver
- New Queued Serial Peripheral Interface (QSPI) HAL Driver
- Enhancements to the MAX 10 ADC HAL Driver
- Nios II GNU toolchain upgraded to v4.9.1
- Improved support for link time optimization (-flto)
- More control over global pointer optimization using -mgpopt=[none, local, global, data, all]
- Null pointer check (new in GNU v4.9.1) can be disabled with --fno-delete-null-pointer-checks
- Nios II Linux kernel and toolchain components have been accepted upstream
High-profile issues resolved:
- EPCQ HAL driver issues corrected
- Custom newlib generator fixed in Windows Nios II terminal
- stdin now working correctly on Windows
The last version of the Nios II is 14.0 and it is named Nios II Classic. Nios II versions after this build are called Nios II Gen2.
- Options for a 64-bit address range
- Optional peripheral memory region
- Faster and more deterministic arithmetic instructions
The list of new IP includes:
- HPS Ethernet converter IPs - These allow you to assign the HPS Ethernet I/O pins
to FPGA I/O pins and convert them from GMII format to RGMII or SGMII.
Note: This is very helpful if you are pin limited by the HPS I/O.
- New device family-specific IP cores:
- Arria 10 - TPIU trace IP. Trace is the ultimate tool in runtime software debug, much like Signaltap is for FPGA development. This IP enables developers to export the ARM® Cortex™-A9 trace debug signals to external pins so that trace debug modules like Lauterbach® or ARM Dstream, can be connected to the A10 SoC Cortex-A9.
- Max 10 - New IPs that deliver Qsys compatible interfaces to the Max10 ADCs and user flash. These new IPs are used in the Max10 example designs.
The 14.1 release has new example designs that demonstrate:
- Max 10 sleep mode, for low power applications
- Analog I/O for developers that want to use the integrated ADCs
- Dual configuration capability from the Max 10 on-chip configuration flash memory
The Cyclone® V and ArriaV SoC golden system reference designs (GSRDs) have also been updated to support the 14.1 ACDS and SoC EDS releases, this means that they will automatically include the SoC software fixes in 14.1 like the PLL workaround in the preloader.
In this release, 64-bit capability was added to the following tools:
- 64-bit nios2-gdb-server
- 64-bit nios2-flash-programmer
- 64-bit nios2-terminal
There are command line option differences between GCC v4.8.3 and the previously supported version. If you have an existing project created with a previous version, you need to update your makefiles or regenerate your board support package (BSP).
The Free Software Foundation provides the downloads available under GCC Download and full GCC release notes are available under GCC Releases.
The following tools have been upgraded:
- GCC to version
- Link time optimization ([flto]) enabled
- GDB to version 7.7
- newlib to version 1.18
The build environment on the windows host platform has been optimized to give faster build times. For example, building the basic webserver application now takes one-third of the time it used to.
In this release, there is added support for Max10 through the addition of memory initialization and bootload support for the user flash memory.
There is a beta version of a new file conversion utility, called alt-file-convert, that makes it easier to get your data into the correct format for loading into flash.
HAL software and bootloader support for the upgraded EPCQ soft IP peripheral has been added.
The EPCQ IP core has been upgraded to add support for x4 mode and L devices, giving faster access to the EPCQ device from Nios or other FPGA based masters.
The Nios II Software Build Tools (SBT) v14.0 only supports 64-bit host systems.
The following Nios II utilities have been moved to the Quartus II product:
In earlier versions of the Nios II EDS, if run-time stack checking was enabled, the Nios II system could become unresponsive. This issue is resolved in v14.0.
In earlier versions of the Nios II EDS, the compiler did not correctly support long jumps (outside a 256-MB address range). This issue is resolved in v14.0.
To fully support Floating Point Hardware 2, you must recompile the newlib C library. In the Nios II EDS v13.1, the linker failed to link the recompiled C library with the application. This issue is resolved in v14.0.
Starting with v14.0, the Nios II EDS supports the Address Span Extender and IRQ Bridge cores.
In v14.0, the Nios II processor core includes a preview implementation of the Nios II Gen2 processor core, supporting Altera's latest device families. The Nios II Gen2 processor core delivers size and performance similar to the original Nios II processor, and is compatible with Nios II Classic processor code at the binary level.
The tool flow and HAL include options to support Nios II Gen2 features. The workflow for generating BSPs and building software is the same, but BSPs generated for the Nios II Classic processor must be regenerated.
The Nios II Hardware Abstraction Layer (HAL) is extended to support the following Nios II Gen2 features:
- A 32-bit address range
- Peripheral (uncached) memory regions
- ECC protection on data cache and TCMs in the Nios II/f core
MAX 10 FPGA devices are supported by the Nios II Gen2 processor, but not by the Nios II Classic processor. To implement a Nios II system on a MAX 10 device, you must use the Nios II Gen2 processor core.
The Altera On-chip Flash memory component, introduced in 14.0, enables Avalon-MM access to on-chip MAX 10 user flash memory. With this component, the Nios II boot copier can copy code to RAM from the MAX 10 user flash memory.
The HAL adds basic driver support for the MAX 10 analog to digital (A/D) converter.
The Altera device programming utilities are updated to support programming the MAX 10 user flash memory.
Arria 10 FPGA devices are supported by the Nios II Gen2 processor, but not by the classic Nios II processor. To implement a Nios II system on an Arria 10 device, you must use the Nios II Gen2 processor core.
There are command line option differences between GCC v4.7.3 and the previously supported version. If you have an existing project created with a previous version, you need to update your makefiles or regenerate your board support package (BSP).
For details about the Nios II GCC 4.7.3 implementation, refer to Nios II GNU toolchain upgrade from GCC 4.1.2 to GCC 4.7.3 in the Altera Knowledge Base.
The Free Software Foundation provides a guide to porting to GCC 4.7, documenting common issues. This guide can be found on GCC, the GNU Compiler Collection, under Porting to GCC 4.7. Full GCC release notes are available under GCC Releases.
To take advantage of software support for the Floating Point Hardware 2 instructions, include altera_nios_custom_instr_floating_point_2.h , which forces GCC to call newlib math functions (rather than GCC built-in math functions). Altera recommends that you recompile newlib with for optimum performance.
The Nios II software build tools (SBT) add individual –mcustom commands to the makefile to support the Floating Point Hardware 2 custom instructions.
By default, ECC is not enabled on reset. Therefore, software must enable ECC protection. Software can also inject ECC errors into RAM data bits to support testing of the ECC exception handler and event bus.
The Nios II Hardware Abstraction Layer (HAL) is extended to support ECC initialization and exception handling.
The upgraded boot copier is called the universal boot copier.
The Nios II boot copier copies the application binaries from flash devices to volatile memory. The flash memory is laid out with the FPGA image at the lowest memory address, followed by the Nios II application binary images.
In previous product releases, the FPGA image size was fixed for each device family. However, for devices in the Cyclone V, Stratix V, and Arria V families, the image size varies depending on the following variables:
- Flash type: Quad-output (EPCQ) or single-output (EPCS) Enhanced Programmable Configuration device
- Flash device capacity: 128 or 256 Mbits
- Serial peripheral interface (SPI) configuration: ×1 or ×4
- Device layout: single or cascaded
It is difficult for the boot copier to identify the current combination so that it can use the appropriate image size, and any algorithm might fail to support future configurations.
To solve this problem, a header is added to the FPGA image to specify the image size. By using the image size from the header, the universal boot copier can work with any flash configuration in current or future devices.
The sof2flash utility is updated to support the universal boot copier.
This change does not impact to the ability of the FPGA control block to automatically program the FPGA image at power-on.
The following list contains known issues and errata, if any:
- There is a minor difference in the Nios II Gen2 processor cache behavior that might affect developers who choose to leverage the non-standard cache behavior of the classic processors in their applications.