|Intel® Stratix® 10 Power Management User Guide||https://www.altera.com/documentation/wtw1443764386078.html|
|Intel® Stratix® 10 GX, MX, TX, and SX Device Family Pin Connection Guidelines||https://www.altera.com/documentation/lod1484643014646.html|
|Intel® Stratix® 10 Device Datasheet||https://www.altera.com/documentation/mcn1441092958198.html|
|Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines||https://www.altera.com/documentation/wtw1404286459773.html|
|Intel® Arria® 10 Device Datasheet||https://www.altera.com/documentation/mcn1413182292568.html|
|Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines||https://www.altera.com/documentation/osf1485840198234.html|
|Intel® Cyclone® 10 GX Device Datasheet||https://www.altera.com/documentation/muf1488511478825.html|
|Quad-Comparator Circuit Provides Power-Down Sequencing At Low Cost||How2Power Today, Josh Mandelcorn|
The requirements in this document must be followed to prevent unnecessary current draw to the FPGA device. Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 devices do not support 'Hot-Socketing' except under the conditions stated in the table below. The tables below also show what the unpowered pins can tolerate during power-up and power-down sequences.
|Pin Type||Tristate||Drive to GND||Drive to VCCIO||Driven with < 1.1 Vp-p||Tristate||Drive to GND||Drive to VCCIO||Driven with < 1.1 Vp-p|
|LVDS I/O banks||√||√||√1||-||√||√||√1||-|
|Differential Transceiver pins||√||√||-||√2||√||√||-||√2|
The power rails in Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 devices are each divided into three groups. Refer to the Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines, Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines, Intel® Stratix® 10 GX, MX, SX, and TX Device Family Pin Connection Guidelines, and the Intel® Stratix® 10 Power Management User Guide for additional details.
The diagram below illustrates the voltage groups of the Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 devices and their required power-up sequence.
|Intel® Cyclone® 10 GX||Intel® Arria® 10||Intel® Stratix® 10|
VCCRT_GXE (TX device)
VCCRTPLL_GXE (TX device)
VCCH_GXE (TX device)
VCCCLK_GXE (TX device)
All power rails in Group 1 must ramp up (in any order) to a minimum of 90% of their respective nominal voltage before the power rails from Group 2 can start ramping up.
The power rails within Group 2 can ramp up in any order after the last power rail in Group 1 ramps to the minimum threshold of 90% of its nominal voltage. All power rails in Group 2 must ramp to a minimum threshold of 90% of their nominal value before the Group 3 power rails can start ramping up.
The power rails within Group 3 can ramp up in any order after the last power rail in Group 2 ramps up to a minimum threshold of 90% of their full value.
For Intel® Cyclone® 10 GX and Intel® Arria® 10 devices, you can combine and ramp up Group 3 power rails with Group 2 power rails if the two groups share the same voltage level and the same voltage regulator as Group 2 power rails VCCIO, VCCPGM, and VCCIO_HPS.
All power rails must ramp up monotonically. The power-up sequence should meet either the standard or the fast Power On Reset (POR) delay time. The POR delay time depends on the POR delay setting you use.
|Intel® Stratix® 10||AS (Normal mode), AVST ×8, AVST ×16, AVST ×32, NAND, SD/MMC||12||20||ms|
|Intel® Stratix® 10||AS (Fast mode)||2||6.5||ms|
Intel® Cyclone® 10 GX
Intel® Arria® 10
Intel® Cyclone® 10 GX
Intel® Arria® 10
For configuration via protocol (CvP), the total TRAMP must be less than 10 ms from the first power supply ramp-up to the last power supply ramp-up. Select a fast POR delay setting to allow sufficient time for the PCI Express® ( PCIe® ) link initialization and configuration. The power-up sequence must meet either the standard or fast POR delay time depending on the POR delay setting you use.
Intel's FPGAs need to follow certain requirements during a power-down sequence. The power-down sequence can be a controlled power-down event via an on/off switch or an uncontrolled event as with a power supply collapse. In either case, you must follow a specific power-down sequence. Below are four power-down sequence specifications. They are either Recommended (one), Required (two), or Relaxed (one). To comply with Intel® ’s FPGA Power-Down requirements, the Recommended option is best.
Recommended Power-Down Ramp Specification
This is the best option to minimize power supply currents.
- Power down all power rails fully within 100 ms.
- Power down power supplies within the same Group in any order.
- Before Group 2 supplies power down, power down all Group 3 supplies within 10% of GND.
- Before Group 1 supplies power down, power down all Group 2 supplies within 10% of GND.
- The maximum voltage differential between any Group 3 supply and any Group 2 supply is 1.92 V.
- Ensure that the newly combined power rails do not cause any driving of unpowered GPIO or transceiver pins.
- Ensure that the newly combined power rails do not violate any power-down sequencing specification due to device (third party) leakage; maintain the Required Voltage Differential Specification.
During the power-up/down sequence, the device output pins are tri-stated. To ensure long term reliability of the device, Intel recommends that you do not drive the input pins during this time.
Required Power-Down Ramp Specification
In cases where power supply is collapsing or if the recommended specification cannot be met, the following PDS sequence is required.
- Power down all power rails fully within 100 ms.
- As soon as possible, disable all power supplies.
- Tri-state Group 1 supplies, and do not drive them actively to GND.
- If possible, drive or terminate Group 2 and Group 3 supplies to GND.
- Ensure no alternative sourcing of any power supply exists during the power-down sequence; reduce all supplies monotonically and with a consistent RC typical decay.
- By the time any Group 1 supply goes under 0.35 V, all Group 2 and Group 3 supplies must be under 1.0 V.
Required Voltage Differential Specification
To not excessively overstress device transistors during power-down, there is an additional voltage requirement between any two power supplies between different power groups during power-down:
ΔV < ΔVnom + 500 mV
- Power down all power rails fully within 100 ms.
- For example, if Group 1 Voltage = 0.9 V, Group 2 Voltage = 1.8 V, and Group
3 Voltage = 3.0 V, then:
G3Vnom = 3.0 V
G2Vnom = 1.8 V
G2Vnom = 1.8 V
G1Vnom = 0.9 V
G3Vnom = 3.0 V
G1Vnom = 0.9 V
(G3V – G2V)nom = 1.2 V (G2V – G1V)nom = 0.9 V (G3V – G1V)nom = 2.1 V (G3V – G2V) <= 1.2 V + .5 V (G2V – G1V) <= 0.9 V + .5 V (G3V – G1V) <= 2.1 V + .5 V (G3V – G2V) <= 1.7 V (G2V – G1V) <= 1.4 V (G3V – G1V) <= 2.6 V
- To meet this voltage differential requirement, ramp down all power supplies as soon as possible according to the Required Power-Down Ramp Specification.
Relaxed Power-Down Duration Specification
For supplies being powered down with no active termination, voltage reduction to GND slows down as supply approaches 0 V. In this case, the 100 ms power requirement is relaxed - measure it when supply reaches near GND.
- Ensure all Group 1 supplies reach < 100 mV within 100 ms.
- Ensure all Group 2 and Group 3 supplies reach < 200 mV within 100 ms.
These controllers provide the necessary power-up/down sequence control functions. These controllers can dynamically monitor and scale the regulator's output voltage, and supervise fault conditions such as over voltage or under voltage. To program the power management controller, typically a PMBus or I2C interface is used to connect to an intelligent host such as the system's microprocessor.
PPMC can be an optimal solution for systems in which up-time and fault tolerance are critical features and voltage monitoring and fault reporting are essential system requirements.
A single channel of the PPMC typically provides the following features:
- Differential sense line inputs to remotely monitor the load voltage.
- Digital-to-Analog Converter (DAC) outputs to trim the regular output voltages. The DAC outputs drive the regulator's feedback input (fb) and control the regulator's output voltage.
- Enable Outputs (EN1, EN2, ...ENn) that drive the voltage regulator's Enable Inputs (en). The regulator's enable inputs control the desired power-up/down sequence.
Typically, PPMC devices have multiple channels so that a single controller can sequence multiple regulators. If more channels are required than what is offered by a single device, then multiple devices can be cascaded. A separate host interface (PMBus or I2C) is used to connect the system processor and the PPMC to manage the controller software and programming.
Consult your power module vendor for more information about PPMC.
Consult your power module vendor for more information about multiple supply sequencer ICs.
The RC ramp-up/down voltage is compared with preset reference voltage levels to generate a series of sequenced power enable outputs to control the voltage regulators.
The power-on event triggers the capacitor charging. As the capacitor voltage rises above each of the preset reference voltage levels, the power enable outputs are sequentially turned on. Similarly, for the power-down event, the discharging of the capacitor causes the power enable outputs to turn off in the reverse sequential order.
A system standby voltage VCC_stby is always present to power the comparator U1A. A reference voltage Vref is generated from VCC_stby through resistor dividers R3 and R4. Vref is the reference voltage for the inverting input of comparator U1A. A more accurate Vref can be generated using a precision trimmed zener diode in place of resistor R4. The resistor ladder network consists of resistors R7, R8, R9, and R10. This ladder network further divides the reference voltages V3, V2, and V1. Comparator (U1B, U1C, and U1D) outputs drive the associated regulator enables (En_reg3, En_Reg2, En_Reg1). These outputs turn On/Off the voltage regulators (not shown). Switch S1 is the system power On/Off switch.
Power ONInitially, the power sequencer circuit is not operational because the power switch S1 is open. As a result, all regulator enables (En_Reg1, En_Reg2, and En_Reg3) are low. As the regulator enables drive the voltage regulators, all voltage regulators are turned off.
- When switch S1 is closed, the system turns on and the voltage VCC charges the capacitor C1 to voltage level Vin.
- C1 is charged through resistor R1. Voltage level Vin depends on the values of R1 and R2 which form voltage divider and Vin = (R2/(R1+R2))*VCC. R1 and R2 are selected such that the value of Vin is slightly higher than comparator U1A's reference voltage Vref.
- When the value of Vin rises above Vref, comparator U1A's output goes high and capacitor C4 starts charging through resistor R5.
- Resistors R5 and R6 set the ramp voltage Vramp. Resistor R5 and capacitor C4 define the time constant for the ramp rate of Vramp. Vramp is the input voltage to the non-inverting inputs of comparators U1B, U1C, and U1D. As Vramp rises above the voltage references (V1, V2, and V3), it sequentially trips comparators U1D, U1C, and U1B, turning on regulator enables En_Reg1, En_Reg2, and En_Reg3.
- The order of the power-down sequence is reverse of the power-up sequence.
- When switch S1 is opened, the system starts shutting down. Capacitor C1 starts discharging through R2. R2 and C1 set the decay rate of Vin during the power-down cycle.
- When Vin falls below Vref, comparator U1A's output turns off. This discharges Vramp through the parallel combination of R5 and R6.
- As Vramp discharges below V3, V2, and V1, the comparators U1B, U1C and U1D sequentially turn off their regulator enables.
This example circuit can be easily expanded to support more regulator enable (reg_en) outputs.
To expand the circuit, add more comparators and extend the resistor ladder network to generate additional reference voltage comparison points (for example, V4, V5, etc). Also, increase the Vramp charging/discharging rate to allow more time between the additional regulator enables. This time delay is controlled by the time constant determined by R5, R6, and C4.
Sudden loss of power events such as a utility grid blackout, accidental removal of the system power cable, or other uncontrolled loss of power events can create difficult power management scenarios for the system designer. To manage these types of exceptions with Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 devices, ensure the power management design incorporates these features:
- Loss of power detection
- Hold-up capacitor (potentially needed) to keep the Power Management Circuitry operational during shutdown
- Reset logic to the FPGA and system to minimize power consumption during shutdown
- Rapid discharge circuit for each power group to minimize power-down time
The following figure shows a conceptual implementation for managing uncontrolled power loss events.
The Power Management Circuit (in the above diagram) is powered directly from the VIN high-side DC input voltage, but can operate down to 5 V. You may need CHOLD to maintain sufficient charge to keep the Power Management Circuitry operational during loss of power events. CDECAP Group 1-3 represents the total decoupling capacitance associated with each power rail grouping. RDISCHARGE 2-3 and its associated power FETs enable fast discharging of each power group voltage to 0 V when you initiate a shutdown sequence. The fast discharging circuit speeds up the power-down cycle of each rail (as the natural RC discharge decay is very slow) and can also define the order in which the rails discharge by trimming RDISCHARGE. Without the fast discharge circuit, the shutdown time could be very long, requiring a larger capacitance for CHOLD.
Theory of Operation
While the system is running, the high-side DC input is maintained at VIN +/-10% tolerance. The power loss detection circuit continuously monitors the DC input for a loss of power event. This detection circuit can be a simple comparator with a reference voltage set to a threshold slightly below the -10% threshold, or it can be an Analog-to-Digital Converter (ADC) employing multiple successive samplings to discriminate against false power interruptions.
When a valid loss of power event occurs, the detection circuit generates a reset to the system. The reset signal pulls the FPGAs’ NCONFIG signal low to reduce the device’s operational current to just its static quiescent value. Concurrently, the Power Management Circuit is triggered to initiate a shutdown sequence. This reduces the value of CHOLD needed to support the Power Management Circuitry during the shutdown process.
The ∆t time that the Power Management Circuit has to perform a graceful power-down is dependent on the total power consumption of the system and CHOLD capacitor needed to maintain reliable system power. While the individual power groups are being disabled in reverse sequential order, the FET for each particular group is also successively turned on to facilitate a rapid discharge of their respective power rail to ground through the RDISCHARGE resistors. You must properly size the discharge FET and resistor to handle the instantaneous discharge current through it. The discharge resistor must be able to handle the single pulse power load for the duration of the discharge time. You can determine this from the data sheet of the selected resistor. The data sheet typically provides this data as a graph plotting the Maximum pulse load power versus the Pulse duration for various resistor package sizes. Determine the value of CHOLD from the energy stored in the capacitor and the total power required to maintain system operation, calculated from the following equations:
E = Energy stored in the capacitor in Joules
P = Power in Watts
V = Voltage in Volts
C = Capacitance in Farads
t = Time in Seconds
Eff = Efficiency percentage of the regulator
Consider an FPGA system that has total quiescent current of 25 A when the system is under reset (FPGA leakage and total system standby current), and the hold time of the capacitor needs to be 1 ms as the voltage drops from 10 V to 5 V. Also, assume that the voltage rail is 0.9 V.
Determine the CHOLD capacitance required for the Power Management Controller to maintain operation so that you can complete a proper power-down sequence.
CHOLD = (2 * 25 A * 0.9 V * .001 s) / (0.85 * (10^2 -5^2)) = 0.045 / 63.75 µF = 706 µF
Take care when selecting a design for controlling the sequence during a fault condition. Non-sequential power-down controllers can violate the power-down specification of the Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 devices. External active termination and trimming RDISCHARGE can alleviate this problem (refer to the "Fault Tolerant Block Diagram (Required Version)" in Managing Uncontrolled Loss of Power Events).
There are voltage regulators on the market that clamp the output to GND in the event of a fault condition. This type of control can be disabled. Group 2 can be clamped only if it is clamped with the same control signal as Group 3. Otherwise, make sure that regulators in Group 1 and Group 2 do not have this option enabled.
A series resistor can be used to help limit current if necessary. The worst case assumption is that VCCN is ~0 V. If diode D2 is biased by 1.8 V, impedance into VCCN is extremely low (refer to the figure below).
Fully configure the transceiver block before driving or having any activity on the Intel® Cyclone® 10 GX and Intel® Arria® 10 device transceiver pins.
Intel® Stratix® 10 device transceiver pins do not support ‘Hot-Socketing’ although these transceiver pins can tolerate 1.1 Vp-p during power-up or power-down. This applies to L-Tile and H-Tile devices only.
|2018.04.13||Made the following changes:
|2018.02.28||Made the following changes:
|2017.05.08||Made the following changes:
|2016.10.31||Made the following changes:
|2016.09.20||Made the following change:
|2016.06.16||Made the following changes:
|2015.1.02||Made the following change:
|2013.09.06||Initial release to MOLSON.|