The Intel® Stratix® 10 LL 40GbE IP core provides a simulatable testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware. You can download the compiled hardware design to the Stratix 10 GX Transceiver Signal Integrity Development Kit. The testbench and demonstration design example are available for a wide range of parameters. However, they do not cover all possible parameterizations of the Stratix® 10 LL 40GbE IP Core.
In addition, for most IP core variations, Intel® provides a compilation-only example project that you can use to quickly estimate IP core area and timing.
The hardware configuration and test files (the hardware design example) are located in <design_example_dir>/hardware_test_design. The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench. The compilation-only example design is located in <design_example_dir>/compilation_test_design.
The simulation design example top-level test file is basic_avl_tb_top.sv. This file instantiates and connects an ATX PLL. It includes a task to send and receive 10 packets. The simulation design example for 40GBASE-KR4 variations also exercises auto-negotiation and link training, if enabled.
|Testbench and Simulation Files|
|basic_avl_tb_top.sv||Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets. The testbench also implements auto-negotiation and link training if enabled in a 40GBASE-KR4/CR4 DUT.|
The ModelSim script to run the testbench.
The Synopsys VCS script to run the testbench.
The Stratix® 10 LL 40GbE hardware design example includes the following components:
- Stratix® 10 LL 40GbE IP core.
- Client logic that coordinates the programming of the IP core, and packet generation and checking.
- ATX PLL to drive the device transceiver channel clocks.
- IOPLL to generate a 100 MHz clock from a 50 MHz input clock to the hardware design example.
- JTAG controller that communicates with the Intel® System Console. You communicate with the client logic through the System Console.
|eth_ex_40 g.qpf||Quartus® Prime project file.|
|eth_ex_40 g.qsf||Quartus project settings file.|
|eth_ex_40 g.sdc||Synopsys Design Constraints file. You can copy and modify this file for your own Stratix® 10 LL 40GbE design.|
|eth_ex_40 g.v||Top-level Verilog HDL design example file.|
|common/||Hardware design example support files.|
Main file for accessing System Console.
Follow these steps to generate the hardware design example and testbench:
- In the
Quartus® Prime Pro Edition, click File > New Project Wizard to create a new
Quartus® Prime project, or
File > Open Project to open an existing
Quartus® Prime project. The
wizard prompts you to specify a device family and device.
Note: The design example overwrites the selection with the device on the target board. You specify the target board from the menu of design example options in the Example Design tab (Step 8). At the time of publication (2017.05.08), only a single target board is available, the design example DUT if you select an H-tile device is 1SG280HU3F50E3VGS1, and the design example DUT if you select an L-tile device is 1SG280LU3F50E3VGS1.
- In the IP Catalog, locate and select Low Latency 40 G Ethernet. The New IP Variation window appears.
- Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
- Click OK. The parameter editor appears.
- On the IP tab, specify the
parameters for your IP core variation.
Note: The Stratix® 10 LL 40GbE design example does not simulate correctly and does not function correctly in hardware for the following selections:
Note: The Quartus Prime Pro 17.1 Stratix 10 ES Editions software does not provide hardware support for 40GBASE-KR4/CR4 variations of this IP core. Therefore, the hardware test design for these variations does not function correctly in hardware.
- Use external TX MAC PLL
- Enable preamble pass-through turned on
- Ready latency set to the value of 3
- Enable TX CRC insertion turned off
- On the Example Design tab, under Example Design Files, select the Simulation option to generate the testbench, and select the Synthesis option to generate the compilation-only and hardware design examples.
- On the Example Design tab, under Generated HDL Format, only Verilog HDL is available. This IP core does not support VHDL.
- Under Target Development Kit select the Stratix 10 GX Transceiver Signal Integrity Development Kit. You must ensure your project targets the specific Stratix 10 device on the development board.
- Click the Generate Example Design button. The Select Example Design Directory window appears.
- If you wish to modify the design example directory path or name from the defaults displayed (alt_e40_0_example_design ), browse to the new path and type the new design example directory name (<design_example_dir>).
- Click OK.
Follow these steps to simulate the testbench:
- Change to the testbench simulation directory <design_example_dir>/example_testbench.
- Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table "Steps to Simulate the Testbench".
- Analyze the results. The successful testbench sends ten packets, receives
ten packets, and displays "Testbench complete."
Note: The successful 40GBASE-KR4/CR4 testbench performs auto-negotiation (if enabled) and link training (if enabled) before performing these packet send and receive actions.
Table 3. Steps to Simulate the Testbench Simulator Instructions ModelSim In the command line, type vsim -do run_vsim.do
If you prefer to simulate without bringing up the ModelSim GUI, type vsim -c -do run_vsim.doNote: The ModelSim® - Intel FPGA Edition simulator does not have the capacity to simulate this IP core. You must use another supported ModelSim simulator such as ModelSim SE.
VCS In the command line, type sh run_vcs.sh
The successful test run displays output confirming the following behavior:
- Waiting for RX clock to settle
- Printing PHY status
- Sending 10 packets
- Receiving 10 packets
- Displaying "Testbench complete."
The following sample output illustrates a successful simulation test run. For a 40GBASE-KR4/CR4 IP core variation, additional auto-negotiation and link training messages display if these features are enabled.
#Waiting for RX alignment #RX deskew locked #RX lane alignment locked #TX enabled #**Sending Packet 1... #**Sending Packet 2... #**Sending Packet 3... #**Sending Packet 4... #**Sending Packet 5... #**Sending Packet 6... #**Sending Packet 7... #**Received Packet 1... #**Sending Packet 8... #**Received Packet 2... #**Sending Packet 9... #**Received Packet 3... #**Sending Packet 10... #**Received Packet 4... #**Received Packet 5... #**Received Packet 6... #**Received Packet 7... #**Received Packet 8... #**Received Packet 9... #**Received Packet 10... #** #** Testbench complete. #** #*****************************************
To compile the hardware design example and configure it on your Stratix 10 device, follow these steps:
- Ensure hardware design example generation is complete.
- In the Intel® Quartus® Prime Pro Edition software, open the Quartus® Prime project <design_example_dir>/hardware_test_design/eth_ex_40 g.qpf.
- On the Processing menu, click Start Compilation.
- After successful compilation, a SRAM object file (.sof) is available for
non-40GBASE-KR4 variations. Follow these steps to program the hardware
design example on the Stratix 10 device:
- On the Tools menu, click Programmer.
- In the Programmer, click Hardware Setup.
- Select a programming device.
- Select and add the Stratix 10 GX Transceiver Signal Integrity Development Kit to which your Quartus® Prime session can connect.
- Ensure that Mode is set to JTAG.
- Select the Stratix 10 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
- In the row with your .sof, check the box for the .sof.
- Check the box in the Program/Configure column.
- Click Start.
After you compile the Stratix® 10 LL 40GbE IP core design example and configure it on your Stratix® 10 device, you can use the Intel® System Console to program the IP core and its embedded Native PHY IP core registers.
To turn on the System Console and test the hardware design example, follow these steps:
- After the hardware design example is configured on the Stratix 10 device, in the Quartus® Prime Pro Edition software, on the Tools menu, click System Debugging Tools > System Console.
- In the Tcl Console pane, type cd hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest.
- Type source main.tcl to open a connection to the JTAG master.
You can program the IP core with the following design example commands:
- chkphy_status: Displays the clock frequencies and PHY lock status.
- chkmac_stats: Displays the values in the MAC statistics counters.
- clear_all_stats: Clears the IP core statistics counters.
- start_pkt_gen: Starts the packet generator.
- stop_pkt_gen: Stops the packet generator.
- loop_on: Turns on internal serial loopback
- loop_off: Turns off internal serial loopback.
- reg_read <addr>: Returns the IP core register value at <addr>.
- reg_write <addr> <data>: Writes <data> to the IP core register at address <addr>.
To generate the design example, you must first set the parameter values for the IP core variation you intend to generate in your end product. Generating the design example creates a copy of the IP core; the testbench and hardware design example use this variation as the DUT. If you do not set the parameter values for the DUT to match the parameter values in your end product, the design example you generate does not exercise the IP core variation you intend.
The testbench sends traffic through the IP core, exercising the transmit side and receive side of the IP core. In the hardware design example, you can program the IP core in internal serial loopback mode and generate traffic on the transmit side that loops back through the receive side.
The Stratix® 10 LL 40GbE testbench is self-contained and does not require you to drive any input signals.
|clk50||Input||Drive at 50 MHz. The intent is to drive this from a 50
Mhz oscillator on the board.
The hardware design example routes this clock to the input of an IOPLL on the device and configures the IOPLL to drive a 100 MHz clock internally.
|clk_ref||Input||Drive at 644.53125 MHz.|
|cpu_resetn||Input||Resets the IP core. Active low. Drives the global hard reset csr_reset_n to the IP core.|
|tx_serial[3:0]||Output||Transceiver PHY output serial data.|
|rx_serial[3:0]||Input||Transceiver PHY input serial data.|
|user_led[7:0]||Output||Status signals. The hardware design example connects
these bits to drive LEDs on the target board. Individual bits
reflect the following signal values and clock behavior:
|0xB0–0xFF||Stratix 10 LL 40GBASE-KR4/CR4 registers|
|0x300–0x9FF||Standard Stratix® 10 LL 40GbE IP core registers.|
|Stratix 10 dynamic reconfiguration registers. Register base address is 0x4000 for Lane 0, 0x4800 for Lane 1, 0x5000 for Lane 2, and 0x5800 for Lane 3.|