The Intel® Arria® 10 or Intel® Cyclone® 10 Hard IP for PCI Express® IP core includes a programmed I/O (PIO) design example to help you understand usage. The PIO example transfers memory from a host processor to a target device. It is appropriate for low-bandwidth applications. The design example includes an Avalon-ST to Avalon-MM Bridge. This component translates the TLPs received on the PCIe® link to Avalon-MM memory reads and writes to the on-chip memory.
This design example automatically creates the files necessary to simulate and compile in the Quartus® Prime software. You can download the compiled design to the Intel® Arria® 10 GX FPGA Development Kit. The design examples cover a wide range of parameters. However, the automatically generated design examples do not cover all possible parameterizations of the PCIe IP Core. If you select an unsupported parameter set, generations fails and provides an error message.
Note: Intel® Cyclone® 10 GX dvelopment kits are not yet available.
In addition, many static design examples for simulation are only available in the <install_dir>/ip/altera/altera_pcie/altera_pcie_a10_ed/example_design/a10 and <install_dir>/ip/altera/altera_pcie/altera_pcie_a10_ed/example_design/c10 directories.
Follow these steps to generate the design from the IP Parameter Editor:
- In the IP Catalog (Tools > IP Catalog) locate and select the Intel® Arria® 10 or Intel® Cyclone® 10 Hard IP for PCI Express.
- Starting with the Quartus® Prime Pro 16.1 software, the New IP Variation dialog box appears.
- Specify a top-level name and the folder for your custom IP variation, and the target device. Click OK
- On the IP Settings tabs, specify the parameters for your IP variation.
- On the Example Designs tab, the
PIO design is available for your IP variation.
Figure 5. Example Design Tab
- For Example Design Files, select the Simulation and Synthesis options.
- For Generated HDL Format, only Verilog is available.
- For Target Development Kit select the Intel® Arria® 10 or Intel® Cyclone® 10 FPGA Development Kit option.
- Click the Generate Example Design button. The software generates all files necessary to run simulations and hardware tests on the Intel® Arria® 10 or Intel® Cyclone® 10 FPGA Development Kit. Click Close when generation completes.
- Click Finish.
- The prompt, Recent changes have not been generated. Generate now?, allows you to create files for simulation and synthesis. Click No to continue to simulate the design example you just generated.
- Change to the testbench simulation directory.
- Run the simulation script for the simulator of your choice. Refer to the table below.
- Analyze the results.
The software application to test the PCI Express Design Example on the Intel® Arria® 10 GX FPGA Development Kit is available on both 32- and 64-bit Windows platforms. This program performs the following tasks:
- Prints the Configuration Space, lane rate, and lane width.
- Writes 0x00000000 to the specified BAR at offset 0x00000000 to initialize the memory and read it back.
- Writes 0xABCD1234 at offset 0x00000000 of the specified BAR. Reads it back and compares.
If successful, the test program displays the message 'PASSED'
Follow these steps to compile the design example in the Quartus Prime software:
- Launch the Quartus Prime software and open <example_design>pcie_example_design.qpf.
- On the Processing > menu,
select Start Compilation.
The timing constraints for the design example and the design components are automatically loaded during compilation.
Follow these steps to test the design example in hardware:
- In the
directory, unzip Altera_PCIe_Interop_Test.zip.
Note: You can also refer to readme_Altera_PCIe_interop_Test.txt file in this same directory for instructions on running the hardware test.
- Install the
Windows Demo Driver for PCIe on the Windows host machine, using altera_pcie_win_driver.inf.
Note: If you modified the default Vendor ID or Device ID specified in the component GUI, you must also modify them in altera_pcie_win_driver.inf.
- In the <example_design> directory, launch the Quartus Prime software and compile the design (Processing > Start Compilation).
- Connect the development board to the host computer.
- Configure the FPGA on the development board using the generated .sof file (Tools > Programmer).
- Open the Windows Device Manager and scan for hardware changes.
- Select the Intel® FPGA listed as an unknown PCI device and point to the appropriate 32- or 64-bit driver (altera_pice_win_driver.inf) in the Windows_driver directory.
- After the driver loads successfully, a new device named Altera PCI API Device appears in the Windows Device Manager.
- Determine the bus, device, and function number for the
Altera PCI API Device listed in
the Windows Device Manager.
Figure 10. Determining the Bus, Device, and Function Number for New PCIe Device
- Expand the tab, Altera PCI API Driver under the devices.
- Right click on Altera PCI API Device and select Properties.
- Note the bus, device, and function number for the device. The following figure shows one example.
- In the <example_desing/software/windows/interop/Altera_PCIe_Interop_Test/Interop_software directory, click Alt_Test.exe.
- When prompted, type the bus, device, and function numbers and
select the BAR number (0-5) you specified when parameterizing the IP core.
Note: The bus, device, and function numbers for your hardware setup may be different.
- The test displays the message, PASSED, if the test is successful.
The Endpoint (DUT) and PIO application (APPS) perform the necessary translation between the PCI Express TLPs and simple Avalon-MM reads and writes to memory.
The PIO testbench includes the following components:
- The Root Port BFM that drives downstream TLPs to the Endpoint.
Note: This Intel Root Port BFM provides a simple method to do basic testing of the Application Layer logic that interfaces to the DUT. However, the testbench and Root Port BFM are not intended to be a substitute for a full verification environment. To thoroughly test your application, obtain commercially available PCI Express verification IP and tools, or do your own extensive hardware testing or both.
- The Generated PCIe Endpoint Variant (DUT) with the parameters you specified. This component drives TLP data received to the PIO application.
- The PIO Application (APPS) component. Along with some additional logic, it translates Avalon-ST data to Avalon-MM data for writes and reads to the on-chip memory.
- For variants up to Gen3 x8, an on-chip memory (MEM) stores data. Gen3 x16 variants include the memory in the APPs component.
- A Development Kit (DK) conduit interface provides access to PCIe control and status signals for debugging using the Arria 10 FPGA GX Development Kit for ES Devices.
The test program writes and reads back data to 0x00000040 in the on-chip memory. It compares data read to the expected result. The test reports, "Simulation stopped due to successful completion" if no errors occur.
The log file, altpcie_monitor_s10_dlhip_tlp_file_log.log records each TLP for both the initial configuration of the PCIe Endpoint and the test program.
The Intel® Quartus® Prime software stores these files in the <IP core directory>/synth/debug/stp/ directory.
- To open the Tcl console, click View > Utility Windows > Tcl Console.
Type the following command in the Tcl console:
source <IP core directory>/synth/debug/stp/build_stp.tcl
To generate the STP file, type the following command:
main -stp_file <output stp file name>.stp -xml_file <input xml_file name>.xml -mode build
- To add this Signal Tap file (.stp) to your project, select Project > Add/Remove Files in Project. Then, compile your design.
- To program the FPGA, click Tools > Programmer.
To start the Signal Tap
Logic Analyzer, click Quartus Prime > Tools >
The software generation script may not assign the Signal Tap acquisition clock in <output stp file name>.stp. Consequently, the Intel® Quartus® Prime software automatically creates a clock pin called auto_stp_external_clock. You may need to manually substitute the appropriate clock signal as the Signal Tap sampling clock for each STP instance.
- Recompile your design.
To observe the state of your IP core, click Run Analysis.
You may see signals or Signal Tap instances that are red, indicating they are not available in your design. In most cases, you can safely ignore these signals and instances. They are present because software generates wider buses and some instances that your design does not include.
|devkit_status[255:0]||Output||The devkit_status[255:0] bus comprises
the following status signals :
|devkit_ctrl[255:0]||Input||The devkit_ctrl[255:0] bus comprises the following
status signals. You can optionally connect these pins to an
on-board switch for PCI-SIG compliance testing, such as bypass
The Intel® Cyclone® 10 GXPCIe IP Core supports 1, 2, or 4 lanes. Each lane includes a TX and RX differential pair. Data is striped across all available lanes.
The Intel® Arria® 10 PCIe IP Core supports 1, 2, 4 or 8 lanes. Each lane includes a TX and RX differential pair. Data is striped across all available lanes.
Transmit output. These signals are the serial outputs of lanes <n>-1–0.
Receive input. These signals are the serial inputs of lanes <n>-1–0.
Refer to Pin-out Files for Intel Devices for pin-out tables for all Intel devices in .pdf, .txt, and .xls formats.
Transceiver channels are arranged in groups of six. For GX devices, the lowest six channels on the left side of the device are labeled GXB_L0, the next group is GXB_L1, and so on. Channels on the right side of the device are labeled GXB_R0, GXB_R1, and so on. Be sure to connect the Hard IP for PCI Express on the left side of the device to appropriate channels on the left side of the device, as specified in the Pin-out Files for Intel Devices.
There are no control registers for the PIO design example. The PCI Express Base Specification 3.0 defines a comprehensive set of configuration, control, and status registers to control and debug the design example.
Made the following changes:
|2017.03.15||16.1.1||Rebranded as Intel.|