The 50GbE IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware. You can download the compiled hardware design to an Arria 10 GT device.
In addition, Intel provides a compilation-only example project that you can use to quickly estimate IP core area and timing.
The hardware configuration and test files (the hardware design example) are located in <design_example_dir>/hardware_test_design. The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench.The compilation-only design example is located in <design_example_dir>/compilation_test_design.
The simulation example design top-level test file is basic_avl_tb_top.sv This file instantiates and connects an ATX PLL. It includes a task, send_packets_50g_avl, to send and receive 10 packets.
|Testbench and Simulation Files|
|basic_avl_tb_top.sv||Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.|
|run_vsim.do||The ModelSim script to run the testbench.|
|run_vcs.sh||The Synopsys VCS script to run the testbench.|
|run_ncsim.sh||The Cadence NCSim script to run the testbench.|
- 50GbE IP core.
- Client logic that coordinates the programming of the IP core and packet generation.
- ATX PLL to drive the device transceiver channels.
- IOPLL to generate a 100 MHz clock from a 50 MHz input clock to the hardware design example.
- JTAG controller that communicates with the System Console. You communicate with the client logic through the System Console.
|eth_ex_50g.qpf||Quartus Prime project file|
|eth_ex_50g.qsf||Quartus project settings file|
|eth_ex_50g.sdc||Synopsys Design Constraints file. You can copy and modify this file for your own 50GbE design.|
|eth_ex_50g.v||Top-level Verilog HDL design example file|
|common/||Hardware design example support files|
Main file for accessing System Console
Follow these steps to generate the hardware design example and testbench:
- Depending on whether you are using the
Quartus® Prime Pro Edition software or the
Quartus® Prime Standard Edition software, perform one of the following
- In the Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Quartus Prime project. The wizard prompts you to specify a device.
- In the Quartus® Prime Standard Edition software, in the IP Catalog (Tools > IP Catalog), select the Arria 10 target device family.
- In the IP Catalog, locate and select 50G Ethernet . The New IP Variation window appears.
- Specify a top-level name for your IP variation and click OK. The parameter editor adds the top-level .qsys (in Quartus® Prime Standard Edition) or .ip (in Quartus® Prime Pro Edition) file to the current project automatically. If you are prompted to manually add the .qsys or .ip file to the project, click Project > Add/Remove Files in Project to add the file.
- In the
Quartus® Prime Standard Edition
software, you must select a specific Arria 10 device in the Device field, or keep the default device the Quartus Prime software proposes.
Note: The hardware design example overwrites the selection with the device on the target board. You specify the target board from the menu of design example options in the Example Design tab (Step 8).
- Click OK. The parameter editor appears.
- On the IP tab, specify the parameters for your IP core variation.
- On the Example Design tab, for
Example Design Files, select the Simulation option to generate the testbench, and select the
Synthesis option to generate the hardware design
example. Only Verilog HDL files are generated.
Note: A functional VHDL IP core is not available. Specify Verilog HDL only, for your IP core design example.
- For Hardware
Board select the Arria 10 GX Transceiver Signal
Integrity Development Kit.
Note: Contact your Intel FPGA representative for information about a platform suitable to run this hardware example.
- Click the Generate Example Design button. The Select Example Design Directory window appears.
- If you wish to modify the design example directory path or name from the defaults displayed ( alt_e50_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).
- Click OK.
- Refer to the KDB Answer How do I compensate for the
jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference
clock? for a workaround you should apply in the hardware_test_design directory in the .sdc file.
Note: You must consult this KDB Answer because the RX path in the 50GbE IP core includes cascaded PLLs. Therefore, the IP core clocks might experience additional jitter in Arria 10 devices. This KDB Answer clarifies the software releases in which the workaround is necessary.
Follow these steps to simulate the testbench:
- Change to the testbench simulation directory <design_example_dir>/example_testbench.
- Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table "Steps to Simulate the Testbench".
- Analyze the results. The successful testbench sends ten packets, receives
ten packets, and displays "Testbench complete."
Table 3. Steps to Simulate the Testbench Simulator Instructions ModelSim In the command line, type vsim -do run_vsim.do
If you prefer to simulate without bringing up the ModelSim GUI, type vsim -c -do run_vsim.doNote: The ModelSim® - Intel FPGA Edition simulator does not have the capacity to simulate this IP core. You must use another supported ModelSim simulator such as ModelSim SE.
NCSim In the command line, type sh run_ncsim.sh VCS In the command line, type sh run_vcs.sh
The successful test run displays output confirming the following behavior:
- Waiting for RX clock to settle
- Printing PHY status
- Sending 10 packets
- Receiving 10 packets
- Displaying "Testbench complete."
The following sample output illustrates a successful simulation test run:
#Ref clock is run at 625 MHz so whole numbers can used for all clock periods. #Multiply reported frequencies by 33/32 to get actual clock frequencies. #Waiting for RX alignment #RX deskew locked #RX lane alignment locked #TX enabled #**Sending Packet 1... #**Sending Packet 2... #**Sending Packet 3... #**Sending Packet 4... #**Sending Packet 5... #**Sending Packet 6... #**Sending Packet 7... #**Received Packet 1... #**Sending Packet 8... #**Received Packet 2... #**Sending Packet 9... #**Received Packet 3... #**Sending Packet 10... #**Received Packet 4... #**Received Packet 5... #**Received Packet 6... #**Received Packet 7... #**Received Packet 8... #**Received Packet 9... #**Received Packet 10... #** #** Testbench complete. #** #*****************************************
To compile the hardware design example and configure it on your Arria 10 GT device, follow these steps:
- Ensure hardware design example generation is complete.
- In the Quartus® Prime software, open the Quartus® Prime project <design_example_dir>/hardware_test_design/eth_ex_50g.qpf.
- Before compiling, ensure you have implemented the workaround from the KDB Answer How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock? if relevant for your software release.
- On the Processing menu, click Start Compilation.
- After you generate a SRAM object file .sof, follow these steps to program the hardware design example on
the Arria 10 device:
- On the Tools menu, click Programmer.
- In the Programmer, click Hardware Setup.
- Select a programming device.
- Select and add the Arria 10 GT board with 25G retimer to your Quartus® Prime session.
- Ensure that Mode is set to JTAG.
- Select the Arria 10 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
- In the row with your .sof, check the box for the .sof.
- Check the box in the Program/Configure column.
- Click Start.
After you compile the 50GbE IP core design example and configure it on your Arria 10 GT device, you can use the System Console to program the IP core and its embedded Native PHY IP core registers.
To turn on the System Console and test the hardware design example, follow these steps:
- After the hardware design example is configured on the Arria 10 device, in the Quartus® Prime software, on the Tools menu, click System Debugging Tools > System Console.
- In the Tcl Console pane, type cd hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest.
- Type source main.tcl to open a connection to the JTAG master.
You can program the IP core with the following design example commands:
- chkphy_status: Displays the clock frequencies and PHY lock status.
- start_pkt_gen: Starts the packet generator.
- stop_pkt_gen: Stops the packet generator.
- loop_on: Turns on internal serial loopback
- loop_off: Turns off internal serial loopback.
- reg_read <addr>: Returns the IP core register value at <addr>.
- reg_write <addr> <data>: Writes <data> to the IP core register at address <addr>.
To generate the design example, you must first set the parameter values for the IP core variation you intend to generate in your end product. Generating the design example creates a copy of the IP core; the testbench and hardware design example use this variation as the DUT. If you do not set the parameter values for the DUT to match the parameter values in your end product, the design example you generate does not exercise the IP core variation you intend.
The testbench sends traffic through the IP core, exercising the transmit side and receive side of the IP core. In the hardware design example, you can program the IP core in internal serial loopback mode and generate traffic on the transmit side that loops back through the receive side.
The 50GbE testbench is self-contained and does not require you to drive any input signals.
|clk50||Input||Drive at 50 MHz. The intent is to drive this from a 50 Mhz oscillator on the board.|
|clk_ref||Input||Drive at 644.53125 MHz.|
|cpu_resetn||Input||Resets the IP core. Active low. Drives the global hard reset csr_reset_n to the IP core.|
|tx_serial[1:0]||Output||Transceiver PHY output serial data.|
|rx_serial[1:0]||Input||Transceiver PHY input serial data.|
|user_led[7:0]||Output||Status signals. The hardware design example connects
these bits to drive LEDs on the target board. Individual bits
reflect the following signal values and clock behavior:
|50GbE IP core registers.|
|Arria 10 dynamic reconfiguration registers. Register base address is 0x4000 for Lane 0 and 0x4400 for Lane 1.|
|2017.11.08||17.0||Added link to KDB Answer that
provides workaround for potential jitter on
Arria® 10 devices due to cascading ATX PLLs in the IP
core. Refer to Generating the Design Example
and Compiling and Configuring the Design Example in Hardware.
Note: This design example user guide has not been updated to reflect minor changes in design generation in Quartus® Prime releases later than the Quartus® Prime software release v17.0.
|2017.05.08||17.0||Initial public release.|