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AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface

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AN-836 | 2017.12.18

RapidIO II Reference Design for Avalon -ST Pass-Through Interface

Introduction

The RapidIO II reference design for the Avalon^® Streaming ( Avalon^® -ST) pass-through interface demonstrates the use of the Avalon^® -ST pass-through interface to implement NWRITE transactions using the RapidIO II IP.

You can use the Avalon^® -ST pass-through interface of the RapidIO II IP to implement RapidIO transaction types not available by our logical layer (for example, message passing and data streaming). Additionally, you can use this interface to implement custom functions not specified by the RapidIO protocol but applicable to a specific system.

The Avalon^® -ST pass-through interface is an optional interface that is generated when you select the Avalon-ST pass-through interface in the Transport and Maintenance page of the RapidIO II IP parameter editor.

Figure 1. RapidIO II Avalon^® -ST Pass-Through Interface Reference Design Block Diagram

The RapidIO II reference design for Avalon^® -ST pass-through interface includes a traffic generator. The traffic generator initiates NWRITE RapidIO transactions and drives the RapidIO II IP Avalon^® -ST source. The design also includes a traffic checker which sinks the RapidIO transactions and is connected to the RapidIO II IP Avalon^® -ST sink.

Requirements

Software Requirements

Intel^® Quartus^® Prime Pro Edition 17.1
RapidIO II IP License
Note: You need the license only if you compile the design or target the design to your device. Alternatively, you can use the free Intel^® FPGA IP Evaluation Mode feature to evaluate licensed Intel FPGA IP cores in simulation and hardware before purchase.

Hardware Requirements

Intel^® Stratix^® 10 GX FPGA Development Board (1SG280LU3F50E3VGS1 with L-Tile transceivers¹)
FMC Loopback Card
Intel^® FPGA Download Cable II
Power Supply

¹ You can target a different device but this will require you to make modifications to the .qsf file.

Features of the RapidIO II Reference Design for the Avalon -ST Pass-Through Interface

The reference design has the following features:

4x Mode
6.250 Gbaud
156.25 MHz Reference Clock
Avalon^® -ST Pass-Through Interface

Downloading and Installing the Reference Design

You can download the reference design from the Design Store. You must have a myAltera account to gain access to the Design Store.

Download the platform archive file srio2_s10_avst_6g_de.par from the Design Store to your chosen directory.
Open the Intel^® Quartus^® Prime software, click File > Open Project.
Browse to select the srio2_s10_avst_6g_de.par file.
Click Open.
The Open Design Template window appears. For Project name, enter srio2_s10_avst_6g_de.

Figure 2. Open Design Template

Click OK.

After you open the srio2_s10_avst_6g_de.par file in the Intel^® Quartus^® Prime software, you can see the following directory structure.

Figure 3. Directory Structure for the Reference Design Example

Table 1. Reference Design Files
File Name	Description
srio2_s10_avst_6g_de.qpf	Intel^® Quartus^® Prime project file containing the list of all the revisions in the project.
srio2_s10_avst_6g_de.qsf	Intel^® Quartus^® Prime settings file containing the assignments and settings for the project.
jtag_timing_template.sdc	Defines the timing constraints for JTAG.
srio2_s10_avst_6g_de.sof	Pre-generated programming file.
top_srio.v	Top-level design file.
traffic_gen.v	Traffic generator module.
traffic_chk.v	Traffic checker module.
stats.v	Statistics collecting module.
top_srio.sdc	Top-level timing constraints file.
srio2.stp	Pre-populated Signal Tap file.
ip/srio	RapidIO II IP sub folder contains all of the required synthesis files for the core.
srio.ip	RapidIO II IP variation file that contains the parameterization of an IP core in your project.
components/atx_pll	Contains all the necessary synthesis files for the ATX PLL.
components/xcvr_rst_ctl	Contains all the necessary synthesis files for the Transceiver Reset Controller.
components/client_decode	Contains all the necessary synthesis files for the Client Decode Platform Designer based subsystems.
components/ip	Contains all of the Client Decode underlying sub IP block IP variation files. Created during the Client Decode system generation and this file is required to compile the design.
atx_pll.ip	Intel^® Stratix^® 10 ATX PLL IP variation file.
xcvr_rst_ctl.ip	Intel^® Stratix^® 10 Transceiver Reset Controller IP variation file.
client_decode.qsys	Platform Designer subsystems contains a JTAG Master and several Avalon^® -MM bridges used to decode the JTAG Avalon^® -MM address for the different Avalon^® -MM slave interface.
basic.tcl	Defines basic register read and write procedures.
lpbk_ctl.tcl	Defines TX to RX PMA buffer serial loopback control.
main_run.tcl	Contains main call to the other .tcl files.
srio_tasks.tcl	Defines the majority of the RapidIO II related functions and procedures for controlling the traffic generator/checker and the statistics collector.

Walkthrough

To run the design, you must have the Intel^® Stratix^® 10 GX FPGA development kit and you must have installed the Intel^® Quartus^® Prime Pro Edition 17.1 software to your computer.

Follow these steps to run the design:

Hardware Setup

Perform the following steps to setup the hardware for the reference design:

Insert the FMC Loopback Card to the FMC port on the Intel^® Stratix^® 10 GX FPGA development board.
Connect the Intel^® FPGA Download Cable II to the Intel^® Stratix^® 10 GX FPGA development board and to your host computer.
Connect the power adapter shipped with the development board to the power supply jack.

Set the DIP switches of the Intel^® Stratix^® 10 GX FPGA development board as specified below:

Table 2. DIP Switch Control Settings
DIP Switch		Schematic Signal Name	Setting
SW8	1	I2C_SDA	ON
	2	I2C_SCL	ON
	3	FPGA_PWRGD	OFF
SW4	1	RZQ_B2M	OFF
SW4	2	SI516_FS	OFF
SW3	1	CLK0_OEn	OFF
	2	CLK0_RSTn	OFF
	3	FACTORY_LOAD	OFF
SW2	1	PCIE_PRSNT2n_x16	OFF
	2	PCIE_PRSNT2n_x8	OFF
	3	PCIE_PRSNT2n_x4	OFF
	4	PCIE_PRSNT2n_x1	OFF
SW6	1	S10JTAG_BYPASSn	OFF
	2	M5JTAG_BYPASSn	OFF
	3	FAJTAG_BYPASSn	ON
SW1	1	MSEL2	ON
SW1	2	MSEL1	ON

Figure 4. DIP Switches Bottom View

Figure 5. DIP Switches Top View

Turn on the power for the Intel^® Stratix^® 10 GX FPGA development board.
The hardware systems is now ready for programming.
Figure 6. Reference Design Hardware Setup

Programming the FPGA

You can program the FPGA by using any of the following methods:

Using a Nios II Command Shell

Perform the following steps to program the FPGA using a Nios^® II command shell:

On the Windows start menu, click All Programs > Quartus installation directory > NIOS II Command Shell <vesrion number>, to start a Nios^® II command shell.

Type the following command at the Nios^® II command shell:

nios2-configure-sof -c “USB-BlasterII [USB-1]” -d 2 sri02_s10_avst_6g_de.sof

Using the Programmer

Perform the following steps to program the FPGA using the Programmer:

Launch the Intel^® Quartus^® Prime software.
Before you begin the FPGA configuration, ensure the following:
1. The Intel^® FPGA Download Cable II driver is installed on the host computer.
2. The board is powered.
3. No other application is accessing the JTAG chain.
Connect the Intel^® FPGA Download Cable II between your host computer USB port and the USB port on the development board.
On the Tools menu, click Programmer.
Click Auto Detect to display the devices in the JTAG chain and select a device.
Right click and select Change File. Then, select the srio2_s10_avst_6g_de.sof file from the project directory and click Open.
Turn on the Program/Configure option for the srio2_s10_avst_6g_de.sof file.
Click Start to download the srio2_s10_avst_6g_de.sof file to the FPGA. Configuration is complete when the progress bar reaches 100%.

Running the Design

When the board is set up and the FPGA is programmed, you can start running the design:

Invoke the system console. This can be done at the Nios^® II command shell or from the Intel^® Quartus^® Prime software GUI.
In the command window, change your directory to system_console by typing the following command :
```
cd system_console
```

Execute the following commands at the system console:

source main_run.tcl
cfig
link
cstats
stats
start
stats

The traffic generator module starts to generate RapidIO NWRITE transactions with a default payload of 64 bytes. The default number of NWRITE transactions is 0xFFFFFFFF (4,294,967,295 decimal). You can stop the traffic generator by entering the stop command. The generated RapidIO transactions are being received at the traffic checker module since all the traffic is looped back through the FMC Loopback Card.
You can view the transactions transmitted and received counts as well as other statistics by entering the link and the stats commands at the system console.
Figure 7. Link Command Execution

Figure 8. Stats Command Execution
Use Signal Tap to view the packet exchange. This reference design includes the Signal Tap file srio2.stp which monitors the gen_tx and the gen_rx interfaces of the RapidIO Avalon^® -ST pass-through interface. The figures below shows the Signal Tap activity.

Figure 9. auto_signaltap_1

Figure 10. auto_signaltap_2

System Console User Interface Commands

Please refer to the below table for the description of the user interface commands:

Table 3. System Console User Interface Commands
Command	Description
r	Toggles the RapidIO II IP reset input signal. Resets the Rapid IO II IP core.
rc	Toggles the Transceiver Reset Controller reset input signal. Resets the transceiver PCS and PMA.
ds	Disables the scrambler and descrambler in the RapidIO II IP core. Use for diagnosis purpose.
es	Enables the scrambler and descrambler.
link	Reports the status of the RapidIO link.
cfig	Enables the Input and Output ports and disables Destination ID checking, randomly accepting all incoming request packets.
start	Programs the number of packets to be transmitted to 0xFFFFFFFF and enables the traffic generator. The generator stops after transmitting 0xFFFFFFFF packets.
stop	Stops the traffic generator.
send	Takes an integer value representing the number of packets to send. For an example, `send 100`: Generates 100 packets.
cstats	Clear statistics counters.
stats	Report statistics counters.
reinit	Toggles the `PORT_DIS` bit of register 0x15C causing an internal re-initialization of the RapidIO II IP. Helps in diagnosing link up issues.
f4x	Forces the RapidIO II IP into 4x mode.
f2x	Forces the RapidIO II IP into 2x mode.
f1x	Forces the RapidIO II IP into 1x mode.
lps	Loop back set, programs the transceivers into serial loopback, TX to RX at the PMA output buffers.
lpc	Clears loop back.
lpt	Clears the transceiver loopback and then sets it again, toggling serial loopback in the PMA output buffers.

Register Address Map

Table 4. Register Address Map
Module	Base Address	Offset	Description
Transceiver Reconfiguration Port at RapidIO II IP	0x0000_0000	Full transceiver PCS and PMA registers	Please refer to the Logical View Register Map of L-Tile transceivers.
Traffic Generator	0x0004_0000	0x0000	Main control [0]- Start traffic [4]- Stop traffic
		0x0004	Packet size [31:0]- Payload byte size. The default value is 64.
		0x0008	Header size [31:0]- Packet header size in bytes. The default value is 12.
		0x000c	IPG size [31:0]- Intel Packet Gap in cycles. IDLE cycles inserted bt the Traffic Generator between the packets at the Avalon^® -ST interface. The default value is 8.
		0x0010	Packets to transmit [31:0]- Packets to be generated.
		0x0014	Source ID [15:0]- Source ID value to be used in composed packets. The default value is 0xCCCC.
		0x0018	Destination ID [15:0]- Destination ID value to be used in composed packets. The default value is 0x5555.
		0x001c	Starting address [31:0]- Starting address use for NWRITE transactions to be generated.
		0x0020	Priority [1:0]- Priority to be used for NWRITE transactions to be generated.
		0x0024	RapidIO II IP Reset Control. [0]- Resets the RapidIO II IP.
		0x0028	Transceiver PCS/PMA Reset Control [0]- Resets the transceiver PCS/PMA.
Statistics Module	0x0005_0000	0x0000	Main Control [0]- Clears statistics
		0x0004	Transmitted packet count
		0x0008	Packets cancelled by transmit side
		0x000c	Packet Accepted Control Symbols transmitted
		0x0010	Packets-Retrys Control Symbols transmitted
		0x0014	Packets-Not-Accepted Control Symbols transmitted
		0x0018	Packet Accepted Control Symbols received
		0x001c	Packet Retrys Control Symbols received
		0x0020	Packets-Not-Accepted Control Symbols received
		0x0024	Packet CRC Errors received
		0x0028	Packets dropped by the Transport Layer
		0x002c	Control Symbol Errors
		0x0030	Base Device ID (small) programmed
		0x0034	Base Device ID (large) programmed
		0x0038	Port Initialized
		0x003c	Link Initialized
		0x0040	Port Ok
		0x0044	Port Error
		0x0048	Four Lanes aligned
		0x004c	Two Lanes aligned
		0x0050	TX Analogreset (one bit per lane)
		0x0054	TX Digitalreset (one bit per lane)
		0x0058	RX Analogreset (one bit per lane)
		0x005c	RX Digitalreset (one bit per lane)
		0x0060	RX is LockedToData (one bit per lane)
		0x0064	RX Sync Status
		0x0068	RX Signal Detect
		0x006c	Reset Controller TX Ready (one bit per lane)
		0x0070	Reset Controller RX Ready (one bit per lane)
Traffic Checker	0x0006_0000	0x0000	Main control [0]- Clears statistics
		0x0004	NREADs count
		0x0008	NWRITEs count
		0x000c	NWRITE_Rs count
		0x0010	SWRITEs count
		0x0014	Flow Control Types count
		0x0018	Maintenance Read Request types
		0x001c	Maintenance Write Requests types
		0x0020	Maintenance Read Response types
		0x0024	Maintenance Write Response types
		0x0028	Maintenance Port Writes
		0x002c	Data Stream Types count
		0x0030	Doorbell Request Types
		0x0034	Message Type count
		0x0038	Response Types No Payload
		0x003c	Message Response Types
		0x0040	Response Types with Payload
RapidIO II IP Register Access	0x0007_0000	Please refer to the Software Interface section in the RapidIO II IP core user guide

Document Revision History for RapidIO II Reference Design for the Avalon -ST Pass-Through Interface

Date	Version	Changes
December 2017	2017.12.18	Initial release.

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