Prior to the software release v16.0, the Low Latency 40-Gbps Ethernet and Low Latency 100-Gbps Ethernet IP cores were not available separately in the IP Catalog. For release notes for the Low Latency 100-Gbps Ethernet IP core for software releases v16.0 and earlier, refer to the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes.
If a release note is not available for a specific IP core version, the IP core has no changes in that version. Information on the latest update releases is in the Intel Quartus Prime Design Suite Update Release Notes.
|Enhanced malformed packet handling.
The IP core now ignores standard flow control pause packets if they are runt packets or have FCS errors. This change does not affect the IP core's handling of priority-based flow control packets.
|The IP core potentially exhibits a behavior change. If you turn on standard flow control, the IP core might not process some incoming pause packets that it would previously have processed. The IP core continues to forward or drop these packets according to the setting in the RX_PAUSE_FWD register at offset 0x706.||Change required for UNH compliance.|
|Added Reed-Solomon forward error correction (RS-FEC) option Enable RX-FEC for CAUI4 for CAUI-4 variations.||If you turn on the new parameter, the IP core implements RS-FEC as defined in IEEE 802.3bj-2014 clause 91.||New feature.|