This chapter describes the features of the logic array block (LAB) in the Stratix® V core fabric.
The LAB is composed of basic building blocks known as adaptive logic modules (ALMs) that you can configure to implement logic functions, arithmetic functions, and register functions.
You can use half of the available LABs in the Stratix® V devices as a memory LAB (MLAB).
The Quartus® Prime software and other supported third-party synthesis tools, in conjunction with parameterized functions such as the library of parameterized modules (LPM), automatically choose the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions.
This chapter contains the following sections:
- ALM Operating Modes
The LABs are configurable logic blocks that consist of a group of logic resources. Each LAB contains dedicated logic for driving control signals to its ALMs.
MLAB is a superset of the LAB and includes all the LAB features.
Each MLAB supports a maximum of 640 bits of simple dual-port SRAM.
You can configure each ALM in an MLAB as either a 64 × 1 or a 32 × 2 block, resulting in a configuration of either a 64 × 10 or a 32 × 20 simple dual-port SRAM block.
Each LAB can drive 30 ALMs through fast-local and direct-link interconnects. Ten ALMs are in any given LAB and ten ALMs are in each of the adjacent LABs.
The local interconnect can drive ALMs in the same LAB using column and row interconnects and ALM outputs in the same LAB.
Neighboring LABs, MLABs, M20K blocks, or digital signal processing (DSP) blocks from the left or right can also drive the LAB’s local interconnect using the direct link connection.
The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility.
There are two dedicated paths between ALMs—carry chain and shared arithmetic chain. Stratix® V devices include an enhanced interconnect structure in LABs for routing shared arithmetic chains and carry chains for efficient arithmetic functions. These ALM-to-ALM connections bypass the local interconnect. The Quartus® Prime Compiler automatically takes advantage of these resources to improve utilization and performance.
Each LAB contains dedicated logic for driving the control signals to its ALMs, and has two unique clock sources and three clock enable signals.
The LAB control block generates up to three clocks using the two clock sources and three clock enable signals. An inverted clock source is considered as an individual clock source. Each clock and the clock enable signals are linked.
De-asserting the clock enable signal turns off the corresponding LAB-wide clock.
The LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide control signals. The MultiTrack interconnect’s inherent low skew allows clock and control signal distribution in addition to data. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for inter- and intra-design block connectivity.
Clear and Preset Logic Control
LAB-wide signals control the logic for the register’s clear signal. The ALM directly supports an asynchronous clear function. You can achieve the register preset through the NOT-gate push-back logic option in the Quartus® Prime software. Each LAB supports up to two clears.
Stratix® V devices provide a device-wide reset pin (DEV_CLRn) that resets all the registers in the device. An option set before compilation in the Quartus® Prime software controls this pin. This device-wide reset overrides all other control signals.
Each ALM contains a variety of LUT-based resources that can be divided between two combinational adaptive LUTs (ALUTs) and four registers.
With up to eight inputs for the two combinational ALUTs, one ALM can implement various combinations of two functions. This adaptability allows an ALM to be completely backward-compatible with four-input LUT architectures. One ALM can also implement any function with up to six inputs and certain seven-input functions.
One ALM contains four programmable registers. Each register has the following ports:
- Synchronous and asynchronous clear
- Synchronous load
Global signals, general-purpose I/O (GPIO) pins, or any internal logic can drive the clock and clear control signals of an ALM register.
GPIO pins or internal logic drives the clock enable signal.
For combinational functions, the registers are bypassed and the output of the look-up table (LUT) drives directly to the outputs of an ALM.
The general routing outputs in each ALM drive the local, row, and column routing resources. Two ALM outputs can drive column, row, or direct link routing connections, and one of these ALM outputs can also drive local interconnect resources.
The LUT, adder, or register output can drive the ALM outputs. The LUT or adder can drive one output while the register drives another output.
Register packing improves device utilization by allowing unrelated register and combinational logic to be packed into a single ALM. Another mechanism to improve fitting is to allow the register output to feed back into the look-up table (LUT) of the same ALM so that the register is packed with its own fan-out LUT. The ALM can also drive out registered and unregistered versions of the LUT or adder output.
The Stratix® V ALM operates in any of the following modes:
- Normal mode
- Extended LUT mode
- Arithmetic mode
- Shared arithmetic mode
Normal mode allows two functions to be implemented in one Stratix® V ALM, or a single function of up to six inputs.
Up to eight data inputs from the LAB local interconnect are inputs to the combinational logic.
The ALM can support certain combinations of completely independent functions and various combinations of functions that have common inputs.
For the packing of 2 five-input functions into one ALM, the functions must have at least two common inputs. The common inputs are dataa and datab. The combination of a four-input function with a five-input function requires one common input (either dataa or datab).
In the case of implementing 2 six-input functions in one ALM, four inputs must be shared and the combinational function must be the same. In a sparsely used device, functions that could be placed in one ALM may be implemented in separate ALMs by the Quartus® Prime software to achieve the best possible performance. As a device begins to fill up, the Quartus® Prime software automatically uses the full potential of the Stratix® V ALM. The Quartus® Prime Compiler automatically searches for functions using common inputs or completely independent functions to be placed in one ALM to make efficient use of device resources. In addition, you can manually control resource use by setting location assignments.
You can implement any six-input function using inputs dataa, datab, datac, datad, and either datae0 and dataf0 or datae1 and dataf1. If you use datae0 and dataf0, the output is either driven to register0, register0 is bypassed, or the output driven to register0 and register0 is bypassed, and the data drives out to the interconnect using the top set of output drivers as shown in the following figure. If you use datae1 and dataf1, the output either drives to register1 or bypasses register1, and drives to the interconnect using the bottom set of output drivers. The Quartus® Prime Compiler automatically selects the inputs to the LUT. ALMs in normal mode support register packing.
If you use datae1 and dataf1 as inputs to a six-input function, datae0 and dataf0 are available for register packing.
The dataf1 input is available for register packing only if the six-input function is unregistered.
In this mode, if the 7-input function is unregistered, the unused eighth input is available for register packing.
Functions that fit into the template, as shown in the following figure, often appear in designs as “if-else” statements in Verilog HDL or VHDL code.
The ALM in arithmetic mode uses two sets of two 4-input LUTs along with two dedicated full adders.
The dedicated adders allow the LUTs to perform pre-adder logic; therefore, each adder can add the output of two 4-input functions.
The ALM supports simultaneous use of the adder’s carry output along with combinational logic outputs. The adder output is ignored in this operation.
Using the adder with the combinational logic output provides resource savings of up to 50% for functions that can use this mode.
Arithmetic mode also offers clock enable, counter enable, synchronous up and down control, add and subtract control, synchronous clear, and synchronous load.
The LAB local interconnect data inputs generate the clock enable, counter enable, synchronous up/down, and add/subtract control signals. These control signals are good candidates for the inputs that are shared between the four LUTs in the ALM.
The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. You can individually disable or enable these signals for each register. The Quartus® Prime software automatically places any registers that are not used by the counter into other LABs.
The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared arithmetic mode.
The two-bit carry select feature in Stratix® V devices halves the propagation delay of carry chains within the ALM. Carry chains can begin in either the first ALM or the fifth ALM in a LAB. The final carry-out signal is routed to an ALM, where it is fed to local, row, or column interconnects.
To avoid routing congestion in one small area of the device when a high fan-in arithmetic function is implemented, the LAB can support carry chains that only use either the top half or bottom half of the LAB before connecting to the next LAB. This leaves the other half of the ALMs in the LAB available for implementing narrower fan-in functions in normal mode. Carry chains that use the top five ALMs in the first LAB carry into the top half of the ALMs in the next LAB in the column. Carry chains that use the bottom five ALMs in the first LAB carry into the bottom half of the ALMs in the next LAB within the column. You can bypass the top-half of the LAB columns and bottom-half of the MLAB columns.
The Quartus® Prime Compiler creates carry chains longer than 20 ALMs (10 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. For enhanced fitting, a long carry chain runs vertically, allowing fast horizontal connections to the TriMatrix memory and DSP blocks. A carry chain can continue as far as a full column.
The ALM in shared arithmetic mode can implement a 3-input add in the ALM.
This mode configures the ALM with four 4-input LUTs. Each LUT either computes the sum of three inputs or the carry of three inputs. The output of the carry computation is fed to the next adder using a dedicated connection called the shared arithmetic chain.
Shared Arithmetic Chain
The shared arithmetic chain available in enhanced arithmetic mode allows the ALM to implement a 3-input adder. This significantly reduces the resources necessary to implement large adder trees or correlator functions.
The shared arithmetic chain can begin in either the first or sixth ALM in a LAB.
Similar to carry chains, the top and bottom half of the shared arithmetic chains in alternate LAB columns can be bypassed. This capability allows the shared arithmetic chain to cascade through half of the ALMs in an LAB while leaving the other half available for narrower fan-in functionality. In every LAB, the column is top-half bypassable; while in MLAB, columns are bottom-half bypassable.
The Quartus® Prime Compiler creates shared arithmetic chains longer than 20 ALMs (10 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. To enhance fitting, a long shared arithmetic chain runs vertically, allowing fast horizontal connections to the TriMatrix memory and DSP blocks. A shared arithmetic chain can continue as far as a full column.
The following techniques are used to manage static and dynamic power consumption within the LAB:
- To save AC power, the Quartus® Prime software forces all adder inputs low when the ALM adders are not in use.
- Stratix® V LABs operate in high-performance mode or low-power mode. The Quartus® Prime software automatically chooses the appropriate mode for the LAB, based on your design and to optimize speed versus leakage trade-offs.
- Clocks represent a significant portion of dynamic power consumption because of their high switching activity and long paths. The LAB clock that distributes a clock signal to registers within a LAB is a significant contributor to overall clock power consumption. Each LAB’s clock and clock enable signals are linked. For example, a combinational ALUT or register in a particular LAB using the labclk1 signal also uses the labclkena1 signal. To disable a LAB-wide clock power consumption without disabling the entire clock tree, use the LAB-wide clock enable to gate the LAB-wide clock. The Quartus® Prime software automatically promotes register-level clock enable signals to the LAB-level. All registers within the LAB that share a common clock and clock enable are controlled by a shared, gated clock. To take advantage of these clock enables, use a clock-enable construct in your HDL code for the registered logic.
|December 2016||2016.12.09||Added description on clock source in the LAB Control Signals section.|
|December 2015||2015.12.21||Changed instances of Quartus II to Quartus Prime.|
|January 2014||2014.01.10||Added multiplexers for the bypass paths
and register outputs in the following diagrams:
|December 2012||2012.12.28||Reorganized content and updated template.|
|December 2010||1.1||No changes to the content of this chapter for the Quartus II software 10.1.|
|July 2010||1.0||Initial release.|
The embedded memory blocks in the devices are flexible and designed to provide an optimal amount of small- and large-sized memory arrays to fit your design requirements.
The Stratix® V devices contain two types of memory blocks:
- 20 Kb M20K blocks—blocks of dedicated memory resources. The M20K blocks are ideal for larger memory arrays while still providing a large number of independent ports.
- 640 bit memory logic array blocks (MLABs)—enhanced memory blocks that are configured from dual-purpose logic array blocks (LABs). The MLABs are ideal for wide and shallow memory arrays. The MLABs are optimized for implementation of shift registers for digital signal processing (DSP) applications, wide shallow FIFO buffers, and filter delay lines. Each MLAB is made up of ten adaptive logic modules (ALMs). In the Stratix® V devices, you can configure these ALMs as ten 32 x 2 blocks, giving you one 32 x 20 simple dual-port SRAM block per MLAB. You can also configure these ALMs as ten 64 x 1 blocks, giving you one 64 x 10 simple dual-port SRAM block per MLAB.
|Variant||Member Code||M20K||MLAB||Total RAM Bit (Kb)|
|Block||RAM Bit (Kb)||Block||RAM Bit (Kb)|
|Stratix V GX||A3||957||19,140||6,415||4,009||23,149|
|Stratix V GT||C5||2,304||46,080||8,020||5,012||51,092|
|Stratix V GS||D3||688||13,760||4,450||2,781||16,541|
|Stratix V E||E9||2,640||52,800||15,850||9,906||62,706|
There are several considerations that require your attention to ensure the success of your designs. Unless noted otherwise, these design guidelines apply to all variants of this device family.
The Quartus® Prime software automatically partitions the user-defined memory into the memory blocks based on your design's speed and size constraints. For example, the Quartus® Prime software may spread out the memory across multiple available memory blocks to increase the performance of the design.
To assign the memory to a specific block size manually, use the RAM IP core in the IP Catalog.
For the memory logic array blocks (MLAB), you can implement single-port SRAM through emulation using the Quartus® Prime software. Emulation results in minimal additional use of logic resources.
Because of the dual-purpose architecture of the MLAB, only data input and output registers are available in the block. The MLABs gain read address registers from the ALMs. However, the write address and read data registers are internal to the MLABs.
In the true dual-port RAM mode, you can perform two write operations to the same memory location. However, the memory blocks do not have internal conflict resolution circuitry. To avoid unknown data being written to the address, implement external conflict resolution logic to the memory block.
Customize the read-during-write behavior of the memory blocks to suit your design requirements.
The same-port read-during-write mode applies to a single-port RAM or the same port of a true dual-port RAM.
|Output Mode||Memory Type||Description|
|M20K||The new data is available on the rising edge of the same clock cycle on which the new data is written.|
|"don't care"||MLAB||The RAM outputs "don't care" values for a read-during-write operation.|
The mixed-port read-during-write mode applies to simple and true dual-port RAM modes where two ports perform read and write operations on the same memory address using the same clock—one port reading from the address, and the other port writing to it.
|Output Mode||Memory Type||Description|
A read-during-write operation to different ports causes the MLAB registered output to reflect the “new data” on the next rising edge after the data is written to the MLAB memory.
This mode is available only if the output is registered.
|"old data"||M20K, MLAB||
A read-during-write operation to different ports causes the RAM output to reflect the “old data” value at the particular address.
For MLAB, this mode is available only if the output is registered.
|"don't care"||M20K, MLAB||
The RAM outputs “don’t care” or “unknown” value.
|"constrained don't care"||MLAB||
The RAM outputs “don’t care” or “unknown” value. The Quartus® Prime software analyzes the timing between write and read operations in the MLAB.
In the dual-port RAM mode, the mixed-port read-during-write operation is supported if the input registers have the same clock. The output value during the operation is “unknown.”
Consider the power up state of the different types of memory blocks if you are designing logic that evaluates the initial power-up values, as listed in the following table.
|Memory Type||Output Registers||Power Up Value|
|Bypassed||Read memory contents|
By default, the Quartus® Prime software initializes the RAM cells in Stratix® V devices to zero unless you specify a .mif.
All memory blocks support initialization with a .mif. You can create .mif files in the Quartus® Prime software and specify their use with the RAM IP core when you instantiate a memory in your design. Even if a memory is pre-initialized (for example, using a .mif), it still powers up with its output cleared.
Reduce AC power consumption in your design by controlling the clocking of each memory block:
- Use the read-enable signal to ensure that read operations occur only when necessary. If your design does not require read-during-write, you can reduce your power consumption by de-asserting the read-enable signal during write operations, or during the period when no memory operations occur.
- Use the Quartus® Prime software to automatically place any unused memory blocks in low-power mode to reduce static power.
|Maximum operating frequency||
|Capacity per block (including parity bits)||
|Address clock enable||Supported||Supported|
|Simple dual-port mixed width||Supported||—|
|True dual-port mixed width||Supported||—|
|FIFO buffer mixed width||Supported||—|
|Memory Initialization File (.mif)||Supported||Supported|
|Fully synchronous memory||Supported||Supported|
|Asynchronous memory||—||Only for flow-through read memory operations.|
Output ports are cleared.
|Asynchronous clears||Output registers and output latches||Output registers and output latches|
|Write/read operation triggering||Rising clock edges||Rising clock edges|
Output ports set to "new data".
Output ports set to "don't care".
|Mixed-port read-during-write||Output ports set to "old data" or "don't care".||Output ports set to "old data", "new data", "don't care", or "constrained don't care".|
Soft IP support using the Quartus® Prime software.
Built-in support in x32-wide simple dual-port mode.
Soft IP support using the Quartus® Prime software.
|Memory Block||Depth (bits)||Programmable Width|
|MLAB||32||x16, x18, or x20|
|64||x8, x9, x10|
The mixed-width port configuration is supported in the simple dual-port RAM and true dual-port RAM memory modes.
The following table lists the mixed-width configurations of the M20K blocks in the simple dual-port RAM mode.
|Read Port||Write Port|
|16K x 1||8K x 2||4K x 4||4K x 5||2K x 8||2K x 10||1K x 16||1K x 20||512 x 32||512 x 40|
|16K x 1||Yes||Yes||Yes||—||Yes||—||Yes||—||Yes||—|
|8K x 2||Yes||Yes||Yes||—||Yes||—||Yes||—||Yes||—|
|4K x 4||Yes||Yes||Yes||—||Yes||—||Yes||—||Yes||—|
|4K x 5||—||—||—||Yes||—||Yes||—||Yes||—||Yes|
|2K x 8||Yes||Yes||Yes||—||Yes||—||Yes||—||Yes||—|
|2K x 10||—||—||—||Yes||—||Yes||—||Yes||—||Yes|
|1K x 16||Yes||Yes||Yes||—||Yes||—||Yes||—||Yes||—|
|1K x 20||—||—||—||Yes||—||Yes||—||Yes||—||Yes|
|512 x 32||Yes||Yes||Yes||—||Yes||—||Yes||—||Yes||—|
|512 x 40||—||—||—||Yes||—||Yes||—||Yes||—||Yes|
The following table lists the mixed-width configurations of the M20K blocks in true dual-port mode.
|Port A||Port B|
|16K x 1||8K x 2||4K x 4||4K x 5||2K x 8||2K x 10||1K x 16||1K x 20|
|16K x 1||Yes||Yes||Yes||—||Yes||—||Yes||—|
|8K x 2||Yes||Yes||Yes||—||Yes||—||Yes||—|
|4K x 4||Yes||Yes||Yes||—||Yes||—||Yes||—|
|4K x 5||—||—||—||Yes||—||Yes||—||Yes|
|2K x 8||Yes||Yes||Yes||—||Yes||—||Yes||—|
|2K x 10||—||—||—||Yes||—||Yes||—||Yes|
|1K x 16||Yes||Yes||Yes||—||Yes||—||Yes||—|
|1K x 20||—||—||—||Yes||—||Yes||—||Yes|
|Memory Mode||M20K Support||MLAB Support||Description|
You can perform only one read or one write operation at a time.
Use the read enable port to control the RAM output ports behavior during a write operation:
|Simple dual-port RAM||Yes||Yes||
You can simultaneously perform one read and one write operations to different locations where the write operation happens on port A and the read operation happens on port B.
|True dual-port RAM||Yes||—||
You can perform any combination of two port operations: two reads, two writes, or one read and one write at two different clock frequencies.
You can use the memory blocks as a shift-register block to save logic cells and routing resources.
This is useful in DSP applications that require local data storage such as finite impulse response (FIR) filters, pseudo-random number generators, multi-channel filtering, and auto- and cross- correlation functions. Traditionally, the local data storage is implemented with standard flip-flops that exhaust many logic cells for large shift registers.
The input data width (w), the length of the taps (m), and the number of taps (n) determine the size of a shift register (w × m × n). You can cascade memory blocks to implement larger shift registers.
You can use the memory blocks as ROM.
You can use the memory blocks as FIFO buffers. Use the SCFIFO and DCFIFO IP cores to implement single- and dual-clock asynchronous FIFO buffers in your design.
For designs with many small and shallow FIFO buffers, the MLABs are ideal for the FIFO mode. However, the MLABs do not support mixed-width FIFO mode.
This section describes the clocking modes for the Stratix® V memory blocks.
|Clocking Mode||Memory Mode|
|Single-Port||Simple Dual-Port||True Dual-Port||ROM||FIFO|
|Single clock mode||Yes||Yes||Yes||Yes||Yes|
|Read/write clock mode||—||Yes||—||—||Yes|
|Input/output clock mode||Yes||Yes||Yes||Yes||—|
|Independent clock mode||—||—||Yes||Yes||—|
In the single clock mode, a single clock, together with a clock enable, controls all registers of the memory block.
In the read/write clock mode, a separate clock is available for each read and write port. A read clock controls the data-output, read-address, and read-enable registers. A write clock controls the data-input, write-address, write-enable, and byte enable registers.
In input/output clock mode, a separate clock is available for each input and output port. An input clock controls all registers related to the data input to the memory block including data, address, byte enables, read enables, and write enables. An output clock controls the data output registers.
In the independent clock mode, a separate clock is available for each port (A and B). Clock A controls all registers on the port A side; clock B controls all registers on the port B side.
In all clocking modes, asynchronous clears are available only for output latches and output registers. For the independent clock mode, this is applicable on both ports.
If you perform a simultaneous read/write to the same address location using the read/write clock mode, the output read data is unknown. If you require the output read data to be a known value, use single-clock or input/output clock mode and select the appropriate read-during-write behavior in the IP Catalog.
Independent clock enables are supported in the following clocking modes:
- Read/write clock mode—supported for both the read and write clocks.
- Independent clock mode—supported for the registers of both ports.
To save power, you can control the shut down of a particular register using the clock enables.
The embedded memory blocks support byte enable controls:
- The byte enable controls mask the input data so that only specific bytes of data are written. The unwritten bytes retain the values written previously.
- The write enable (wren) signal, together with the byte enable (byteena) signal, control the write operations on the RAM blocks. By default, the byteena signal is high (enabled) and only the wren signal controls the writing.
- The byte enable registers do not have a clear port.
- If you are using parity bits, on the M20K blocks, the byte enable function controls 8 data bits and 2 parity bits; on the MLABs, the byte enable function controls all 10 bits in the widest mode.
- The LSB of the byteena signal corresponds to the LSB of the data bus.
- The byte enables are active high.
|byteena[1:0]||Data Bits Written|
|byteena[3:0]||Data Bits Written|
In M20K blocks or MLABs, when you de-assert a byte-enable bit during a write cycle, the corresponding data byte output appears as either a “don't care” value or the current data at that location. You can control the output value for the masked byte in the M20K blocks or MLABs by using the Quartus® Prime software.
The M20K memory blocks support packed mode.
The packed mode feature packs two independent single-port RAM blocks into one memory block. The Quartus® Prime software automatically implements packed mode where appropriate by placing the physical RAM block in true dual-port mode and using the MSB of the address to distinguish between the two logical RAM blocks. The size of each independent single-port RAM must not exceed half of the target block size.
The embedded memory blocks support address clock enable, which holds the previous address value for as long as the signal is enabled (addressstall = 1). When the memory blocks are configured in dual-port mode, each port has its own independent address clock enable. The default value for the address clock enable signal is low (disabled).
The M20K memory blocks support asynchronous clear on output latches and output registers. If your RAM does not use output registers, clear the RAM outputs using the output latch asynchronous clear.
The clear is an asynchronous signal and it is generated at any time. The internal logic extends the clear pulse until the next rising edge of the output clock. When the clear is asserted, the outputs are cleared and stay cleared until the next read cycle.
ECC allows you to detect and correct data errors at the output of the memory. ECC can perform single-error correction, double-adjacent-error correction, and triple-adjacent-error detection in a 32-bit word. However, ECC cannot detect four or more errors.
The M20K blocks have built-in support for ECC when in x32-wide simple dual-port mode:
- The M20K runs slower than non-ECC simple-dual port mode when ECC is engaged. However, you can enable optional ECC pipeline registers before the output decoder to achieve the same performance as non-ECC simple-dual port mode at the expense of one cycle of latency.
- The M20K ECC status is communicated with two ECC status flag signals—e (error) and ue (uncorrectable error). The status flags are part of the regular output from the memory block. When ECC is engaged, you cannot access two of the parity bits because the ECC status flag replaces them.
ue (uncorrectable error)
|1||0||A correctable error occurred and the error has been corrected at the outputs; however, the memory array has not been updated.|
|1||1||An uncorrectable error occurred and uncorrectable data appears at the outputs.|
If you engage ECC:
- You cannot use the byte enable feature.
- Read-during-write old data mode is not supported.
|December 2015||2015.12.21||Changed instances of Quartus II to Quartus Prime.|
|June 2014||2014.06.30||Removed the term "one-hot" fashion for byte enables operation. The term one-hot indicates that only one bit can be active at a time.|
|June 2012||1.4||Updated Table 2–1 and Table 2–2.|
|December 2010||1.1||No changes to the content of this chapter for the Quartus II software 10.1.|
|July 2010||1.0||Initial release.|
This chapter describes how the variable-precision digital signal processing (DSP) blocks in Stratix® V devices are optimized to support higher bit precision in high-performance DSP applications.
Each Stratix® V variable precision DSP block spans one logic array block (LAB) row height.
The Stratix® V variable precision DSP blocks offer the following features:
- High-performance, power-optimized, and fully registered multiplication operations
- 9-bit, 18-bit, 27-bit, and 36-bit word lengths
- 18 x 25 complex multiplications for FFTs
- Floating-point arithmetic formats
- Built-in addition, subtraction, and 64-bit accumulation unit to combine multiplication results
- Cascading 18-bit and 27-bit input bus to form the tap-delay line for filtering applications
- Cascading 64-bit output bus to propagate output results from one block to the next block without external logic support
- Hard pre-adder supported in 18-bit and 27-bit mode for symmetric filters
- Supports 18-bit and 27-bit with internal coefficient register bank for filter implementation
- 18-bit and 27-bit systolic finite impulse response (FIR) filters with distributed output adder
|Variable Precision DSP Block Resources||Operational Mode||Supported Instance||Pre-adder Support||Coefficient Support||Input Cascade Support||Chainout Support|
|1 variable precision DSP block||Independent 9 x 9 multiplication||3||No||No||No||No|
|Independent 16 x 16 multiplication||2||Yes||Yes||Yes||No|
|Independent 18 x 18 partial multiplication (32-bit)||2||Yes||Yes||Yes||No|
|Independent 18 x 18 multiplication||1||Yes||Yes||Yes||No|
|Independent 27 x 27 multiplication||1||Yes||Yes||Yes||Yes|
|Independent 36 x 18 multiplication||1||No||Yes||No||Yes|
|Two 18 x 18 multiplier adder||1||Yes||Yes||Yes||Yes|
|Two 16 x 16 multiplier adder||1||Yes||Yes||Yes||Yes|
|Sum of 2 square||1||Yes 1||No||No||Yes|
|18 x 18 multiplication summed with 36-bit input||1||No||No||No||Yes|
|2 variable precision DSP blocks||Independent 18 x 18 multiplication||3||No||No||No||No|
|Independent 36 x 36 multiplication||1||No||No||No||No|
|Complex 18 x 18 multiplication||1||Yes||Yes||Yes||Yes|
|Four 18 x 18 multiplier adder||1||Yes||Yes||Yes||No|
|Two 27 x 27 multiplier adder||1||Yes||Yes||Yes||No|
|Two 18 x 36 multiplier adder||1||No||Yes||No||No|
|3 variable precision DSP blocks||Complex 18 x 25 multiplication||1||Yes1||No||No||No|
|4 variable precision DSP blocks||Complex 27 x 27 multiplication||1||Yes||Yes||Yes||No|
Independent Input and Output
18 x 18
Multiplier Adder Mode
18 x 18
Multiplier Summed with 36-bit Input
9 x 9
16 x 16
18 x 18
Multiplier with 32-bit Resolution
27 x 27
36 x 18
|Stratix® V GX||A3||256||768||512||512||256||256||512||256|
|Stratix® V GT||C5||256||768||512||512||256||256||512||256|
|Stratix® V GS||D3||600||1,800||1,200||1,200||600||600||1,200||600|
|Stratix® V E||E9||352||1,056||704||704||352||352||704||352|
You should consider the following elements in your design:
- Operational modes
- Internal coefficient and pre-adder
- Chainout adder
The Quartus® Prime software includes IP cores that you can use to control the operation mode of the multipliers. After entering the parameter settings with the IP Catalog, the Quartus® Prime software automatically configures the variable precision DSP block.
Altera provides two methods for implementing various modes of the Stratix® V variable precision DSP block in a design—using the Quartus® Prime DSP IP cores and HDL inferring.
The following Quartus® Prime IP cores are supported for the Stratix® V variable precision DSP blocks implementation:
The coefficient feature must be enabled when the pre-adder feature is enabled.
The coefficient feature and pre-adder feature can be used independently.
With pre-adder enabled:
The accumulator feature is applicable to the following modes:
- One sum of two 18 x 18 multipliers
- 27 x 27 independent multiplier
- 36 x 18 independent multiplier
- 18 x 18 multiplication summed with 36-bit input mode
- Sum of square mode
You can use the output chaining path to add results from other DSP blocks.
The Stratix® V variable precision DSP block consists of the following elements:
- Input register bank
- Internal coefficient
- Accumulator and chainout adder
- Systolic registers
- Output register bank
The input register bank consists of data, dynamic control signals, and two sets of delay registers.
All the registers in the DSP blocks are positive-edge triggered and cleared on power up. Each multiplier operand can feed an input register or a multiplier directly, bypassing the input registers.
The following variable precision DSP block signals control the input registers within the variable precision DSP block:
In 18 x 18 mode, you can use the delay registers to balance the latency requirements when you use both the input cascade and chainout features.
One feature of the input register bank is to support a tap delay line; therefore, you can drive the top leg of the multiplier input (B) from general routing or from the cascade chain, as shown in the following figures. The Stratix® V variable precision DSP block supports 18-bit and 27-bit input cascading.
Stratix V Devices
The pre-adder supports both addition and subtraction, which you must choose during compilation time.
Each variable precision DSP block has two 18-bit pre-adders. You can configure these pre-adders in the following configurations:
- Two independent 18-bit adders for 18-bit applications
- One 26-bit adder for 27-bit applications
The Stratix® V variable precision DSP block has the flexibility of selecting the multiplicand from either the dynamic input or the internal coefficient.
The internal coefficient can support up to eight constant coefficients for the multiplicands in 18-bit and 27-bit modes. When you enable the internal coefficient feature, COEFSELA/COEFSELB are used to control the selection of the coefficient multiplexer.
A single variable precision DSP block can perform many multiplications in parallel, depending on the data width of the multiplier.
There are two multipliers (upper multiplier and bottom multiplier) per variable precision DSP block. You can configure these two multipliers in several operational modes:
- One 27 x 27 multiplier
- Two 18 x 18 multipliers
- Three 9 x 9 multipliers
The Stratix® V variable precision DSP block supports a 64-bit accumulator and a 64-bit adder.
For Stratix® V devices, you can use the 64-bit adder as full adder.
The following signals can dynamically control the function of the accumulator:
|Zeroing||Disables the accumulator.||0||0||0|
|Preload||Loads an initial value to the accumulator. Only one bit of the 64-bit preload value can be “1”. It can be used as rounding the DSP result to any position of the 64-bit result.||0||1||0|
|Accumulation||Adds the current result to the previous accumulate result.||0||0||1|
|Decimation||This function takes the current result, converts it into two’s complement, and adds it to the previous result.||1||0||1|
There are two systolic registers per variable precision DSP block. If the variable precision DSP block is not configured in systolic FIR mode, both systolic registers are bypassed.
The first systolic register has two 18-bit registers that are used to register the upper multiplier’s two 18-bit inputs. You must clock these registers with the same clock source as the output register bank.
The second set of systolic registers are used to delay the chainout output to the next variable precision DSP block.
The positive edge of the clock signal triggers the 64-bit bypassable output register bank and is cleared after power up.
The following variable precision DSP block signals control the output register per variable precision DSP block:
This section describes how you can configure an Stratix® V variable precision DSP block to efficiently support the following operational modes:
- Independent Multiplier Mode
- Independent Complex Multiplier Mode
- Multiplier Adder Sum Mode
- Sum of Square Mode
- 18 x 18 Multiplication Summed with 36-Bit Input Mode
- Systolic FIR Mode
In independent input and output multiplier mode, the variable precision DSP blocks perform individual multiplication operations for general purpose multipliers.
You can configure each variable precision DSP block multiplier for 9-, 16-, 18-, 27-Bit, or 36 x 18 multiplication.
For some operational modes, the unused inputs require zero padding.
|Configuration||Multipliers per block|
|9 x 9||3|
|16 x 16||2|
|18 x 18 (partial)||2|
|18 x 18||1|
|27 x 27||1|
|36 x 18||1|
In this figure, the inputs for 16-bit independent multiplier mode are data[15..0]. The unused input bits require padding with zero.
For two independent 18 x 18 partial multiplier mode, only 32-bit LSB result for each multiplication operation is routed to the output.
You can efficiently construct an individual 36-bit multiplier with two adjacent variable precision DSP blocks. The 36 x 36 multiplication consists of four 18 x 18 multipliers, as shown in Figure 1 .
The 36-bit multiplier is useful for applications requiring more than 18-bit precision; for example, for the mantissa multiplication portion of very high precision fixed-point arithmetic applications.
The Stratix® V variable precision DSP block provides the means for a complex multiplication.
The Stratix V variable precision DSP block can support the following:
- one 18 x 18 complex multiplier
- one 18 x 25 complex multiplier
- one 27 x 27 complex multiplier
For 18 x 18 complex multiplication mode, you require two variable precision DSP blocks to perform this multiplication.
You can implement the imaginary part [(a × d) + (b × c)] in the first variable precision DSP block, and you can implement the real part [(a × c) – (b × d)] in the second variable precision DSP block.
Stratix® V devices support an individual 18 x 25 complex multiplication mode.
A 27 x 27 multiplier allows you to implement an individual 18 x 25 complex multiplication mode with three variable precision DSP blocks only. The pre-adder feature is automatically enabled for you to implement an individual 18 x 25 complex multiplication mode efficiently.
You can implement an 18 x 25 complex multiplication with three variable precision DSP blocks, as shown in Figure 1
Stratix® V devices support an individual 27 x 27 complex multiplication mode. You require four variable precision DSP blocks to implement an individual 27 x 27 complex multiplication mode.
You can implement the imaginary part [(a x d) + (b x c)] in the first and second variable precision DSP blocks, and you can implement the real part [(a x c) - (b x d)] in the third and fourth variable precision DSP blocks.
You can achieve the difference of two 27 x 27 multiplications by enabling the NEGATE control signal in the fourth variable precision DSP block.
|Mode||Configuration||Number of DSP Blocks Required|
|Two-multiplier Adder Sum||16 x 16||1|
|18 x 18||1|
|27 x 27||2|
|18 x 36||2|
|Four-multiplier Adder Sum||18 x 18||2|
In this figure, for 18-bit multiplier adder sum mode, the input data width is 18 bits and the output data width is 37 bits.
For 16-bit multiplier adder sum mode, the input data width is 16 bits and the unused input bit requires padding with zeroes. The output data width is 33 bits.
The Stratix® V variable precision DSP block can implement one sum of square mode.
You can feed the four 18-bit inputs into the pre-adder block to convert b and d input as two’s complement numbers to perform subtraction, if required.
You can feed each 18-bit pre-adder block output into both multiplicand and multiplier inputs of an 18 x 18 multiplier to generate a square result.
Stratix® V variable precision DSP blocks support one 18 x 18 multiplication summed to a 36-bit input.
Use the upper multiplier to provide the input for an 18 x 18 multiplication, while the bottom multiplier is bypassed.
The data1[17..0] and data1[35..18] signals are concatenated to produce a 36-bit input.
Stratix® V variable precision DSP blocks support the following systolic FIR structures:
In systolic FIR mode, the input of the multiplier can come from three different sets of sources:
- Two dynamic inputs
- One dynamic input and one coefficient input
- One coefficient input and one pre-adder output
In 18-bit systolic FIR mode, the adders are configured as dual 44-bit adders, thereby giving 8 bits of overhead when using an 18-bit operation (36-bit products). This allows a total of 256 multiplier products.
In 27-bit systolic FIR mode, the chainout adder or accumulator is configured for a 64-bit operation, providing 10 bits of overhead when using a 27-bit data (54-bit products). This allows a total of 1,024 multiplier products.
The 27-bit systolic FIR mode allows the implementation of one stage systolic filter per DSP block.
The Stratix® V variable precision DSP block has a total of 14 dynamic control signal inputs. The variable precision DSP block dynamic signals are user-configurable and can be set to toggle or not at run time.
The Stratix® V variable precision DSP block supports 18-bit and 27-bit input cascading.
|NEGATE||Control the operation of the decimation||1|
|LOADCONST||Preload an initial value to the accumulator||1|
|SUB||This signal has two functions:
Controls the internal coefficient select multiplexer along with select signals provided through the MSB of each 18-bit data input
|Variable precision DSP-block-wide clock signals||3|
|Variable precision DSP-block-wide clock enable signals||3|
|Variable precision DSP-block-wide asynchronous clear signals||2|
|Total Count per DSP Block||14|
|December 2015||2015.12.21||Changed instances of Quartus II to Quartus Prime.|
|July 2014||2014.07.22||Reinstated input register bank and systolic registers to the block architecture.|
|December 2010||1.1||No changes to the content of this chapter for the Quartus II software 10.1.|
|July 2010||1.0||Initial release.|
This chapter describes the advanced features of hierarchical clock networks and phase-locked loops (PLLs) in Stratix® V devices. The Quartus® Prime software enables the PLLs and their features without external devices.
The Stratix® V devices contain the following clock networks that are organized into a hierarchical structure:
- Global clock (GCLK) networks
- Regional clock (RCLK) networks
- Periphery clock (PCLK) networks
|Clock Resource||Device||Number of Resources Available||Source of Clock Resource|
|Clock input pins||All||48 single-ended or 24 differential||CLK[0..23][p,n] pins|
|GCLK networks||All||16||CLK[0..23][p,n] pins, PLL clock outputs, and logic array|
|RCLK networks||All||92||CLK[0..23][p,n] pins, PLL clock outputs, and logic array|
||210||DPA clock outputs, PLD-transceiver interface clocks, I/O pins, and logic array|
For more information about the clock input pins connections, refer to the pin connection guidelines.
Stratix® V devices provide GCLKs that can drive throughout the device. The GCLKs serve as low-skew clock sources for functional blocks, such as adaptive logic modules (ALMs), digital signal processing (DSP), embedded memory, and PLLs. Stratix® V I/O elements (IOEs) and internal logic can also drive GCLKs to create internally-generated global clocks and other high fan-out control signals, such as synchronous or asynchronous clear and clock enable signals.
RCLK networks are only applicable to the quadrant they drive into. RCLK networks provide the lowest clock insertion delay and skew for logic contained within a single device quadrant. The Stratix® V IOEs and internal logic within a given quadrant can also drive RCLKs to create internally generated regional clocks and other high fan-out control signals.
Depending on the routing direction, Stratix® V devices provide vertical PCLKs from the top and bottom periphery, and horizontal PCLKs from the left and right periphery.
Clock outputs from the dynamic phase aligner (DPA) block, programmable logic device (PLD)-transceiver interface clocks, I/O pins, and internal logic can drive the PCLK networks.
PCLKs have higher skew when compared with GCLK and RCLK networks. You can use PCLKs for general purpose routing to drive signals into and out of the Stratix® V device.
The Stratix® V devices provide 33 section clock (SCLK) networks in each spine clock per quadrant. The SCLK networks can drive six row clocks in each logic array block (LAB) row, nine column I/O clocks, and two core reference clocks. The SCLKs are the clock resources to the core functional blocks, PLLs, and I/O interfaces of the device.
A spine clock is another layer of routing between the GCLK, RCLK, and PCLK networks before each clock is connected to the clock routing for each LAB row. The settings for spine clocks are transparent. The Quartus® Prime software automatically routes the spine clock based on the GCLK, RCLK, and PCLK networks.
The following figure shows SCLKs driven by the GCLK, RCLK, PCLK, or the PLL feedback clock networks in each spine clock per quadrant. The GCLK, RCLK, PCLK, and PLL feedback clocks share the same routing to the SCLKs. To ensure successful design fitting in the Quartus® Prime software, the total number of clock resources must not exceed the SCLK limits in each region.
This section describes the types of clock regions in Stratix® V devices.
To form the entire device clock region, a source drives a signal in a GCLK network that can be routed through the entire device. The source is not necessarily a clock signal. This clock region has the maximum insertion delay when compared with other clock regions, but allows the signal to reach every destination in the device. It is a good option for routing global reset and clear signals or routing clocks throughout the device.
To form a regional clock region, a source drives a signal in a RCLK network that you can route throughout one quadrant of the device. This clock region provides the lowest skew in a quadrant. It is a good option if all the destinations are in a single quadrant.
To form a dual-regional clock region, a single source (a clock pin or PLL output) generates a dual-regional clock by driving two RCLK networks (one from each quadrant). This technique allows destinations across two adjacent device quadrants to use the same low-skew clock. The routing of this signal on an entire side has approximately the same delay as a RCLK region. Internal logic can also drive a dual-regional clock network.
In Stratix® V devices, clock input pins, PLL outputs, high-speed serial interface (HSSI) outputs, DPA outputs, and internal logic can drive the GCLK, RCLK, and PCLK networks.
You can use the dedicated clock input pins (CLK[0..23][p,n]) for high fan-out control signals, such as asynchronous clears, presets, and clock enables, for protocol signals through the GCLK or RCLK networks.
CLK pins can be either differential clocks or single-ended clocks. When you use the CLK pins as single-ended clock inputs, only the CLK<#>p pins have dedicated connections to the PLL. The CLK<#>n pins drive the PLLs over global or regional clock networks and do not have dedicated routing paths to the PLLs.
Driving a PLL over a global or regional clock can lead to higher jitter at the PLL input, and the PLL will not be able to fully compensate for the global or regional clock. Altera recommends using the CLK<#>p pins for optimal performance when you use single-ended clock inputs to drive the PLLs.
You can drive each GCLK, RCLK, and horizontal PCLK network using LAB-routing and row clock to enable internal logic to drive a high fan-out, low-skew signal.
Every DPA generates one PCLK to the core.
Every three HSSI outputs generate a group of six PCLKs to the core.
The Stratix® V PLL clock outputs can drive both GCLK and RCLK networks.
|Clock Resources||CLK (p/n Pins)|
|Clock Resources||CLK (p/n Pins)|
For Stratix® V PLL connectivity to GCLK and RCLK networks, refer to the PLL connectivity to GCLK and RCLK networks spreadsheet.
Every GCLK, RCLK, and PCLK network has its own clock control block. The control block provides the following features:
- Clock source selection (dynamic selection available only for GCLKs)
- Global clock multiplexing
- Clock power down (static or dynamic clock enable or disable available only for GCLKs and RCLKs)
|inclk and inclk||Any of the four dedicated clock pins on the same side of the Stratix® V device.|
|inclk||PLL counters C0 and C2 from the two center PLLs on the same side of the Stratix® V devices.|
|inclk||PLL counters C1 and C3 from the two center PLLs on the same side of the Stratix® V devices.|
You can select the clock source for the GCLK select block either statically or dynamically using internal logic to drive the multiplexer-select inputs.
When selecting the clock source dynamically, you can select either PLL outputs (such as C0 or C1), or a combination of clock pins or PLL outputs.
You can only control the clock source selection for the RCLK select block statically using configuration bit settings in the configuration file (.sof or .pof) generated by the Quartus® Prime software.
You can set the input clock sources and the clkena signals for the GCLK and RCLK network multiplexers through the Quartus® Prime software using the ALTCLKCTRL IP core.
To drive the HSSI horizontal PCLK control block, select the HSSI output or internal logic .
To drive the DPA horizontal PCLK, select the DPA clock output or internal logic. You can only use the DPA clock output to generate the vertical PCLK to the core.
You can enable or disable the dedicated external clock output pins using the ALTCLKCTRL IP core.
You can power down the GCLK and RCLK clock networks using both static and dynamic approaches.
When a clock network is powered down, all the logic fed by the clock network is in off-state, reducing the overall power consumption of the device. The unused GCLK, RCLK, and PCLK networks are automatically powered down through configuration bit settings in the configuration file (.sof or .pof) generated by the Quartus® Prime software.
The dynamic clock enable or disable feature allows the internal logic to control power-up or power-down synchronously on the GCLK and RCLK networks, including dual-regional clock regions. This feature is independent of the PLL and is applied directly on the clock network.
You cannot use the clock enable and disable circuit of the clock control block if the GCLK or RCLK output drives the input of a PLL.
The clkena signals are supported at the clock network level instead of at the PLL output counter level. This allows you to gate off the clock even when you are not using a PLL. You can also use the clkena signals to control the dedicated external clocks from the PLLs.
Stratix® V devices have an additional metastability register that aids in asynchronous enable and disable of the GCLK and RCLK networks. You can optionally bypass this register in the Quartus® Prime software.
The PLL can remain locked, independent of the clkena signals, because the loop-related counters are not affected. This feature is useful for applications that require a low-power or sleep mode. The clkena signal can also disable clock outputs if the system is not tolerant of frequency overshoot during resynchronization.
PLLs provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.
The Stratix® V device family contains fractional PLLs that can function as fractional PLLs or integer PLLs. The output counters in Stratix® V devices are dedicated to each fractional PLL that support integer or fractional frequency synthesis.
Two adjacent PLLs share 18 C output counters. Any number of C counters can be assigned to each PLL, as long as the total number used by the two PLLs is 18 or less.
The Stratix® V devices offer up to 32 fractional PLLs in the larger densities. All Stratix® V fractional PLLs have the same core analog structure and features support.
|C output counters||18|
|M, N, C counter sizes||1 to 512|
|Dedicated external clock outputs||4 single-ended or 2 single-ended and 1 differential|
|Dedicated clock input pins||4 single-ended or 4 differential|
|External feedback input pin||Single-ended or differential|
|Spread-spectrum input clock tracking||Yes 2|
|Source synchronous compensation||Yes|
|Zero-delay buffer compensation||Yes|
|External feedback compensation||Yes|
|Voltage-controlled oscillator (VCO) output drives the DPA clock||Yes|
|Phase shift resolution||78.125 ps 3|
|Programmable duty cycle||Yes|
|Power down mode||Yes|
The physical counters for the fractional PLLs are arranged in the following sequences:
Stratix® V devices provide PLLs for the transceiver channels. These PLLs are located in a strip, where the strip refers to an area in the FPGA.
The total number of PLLs in the Stratix® V devices includes the PLLs in the PLL strip. However, the transceivers can only use the PLLs located in the strip.
The following figures show the physical locations of the fractional PLLs. Every index represents one fractional PLL in the device. The physical locations of the fractional PLLs correspond to the coordinates in the Quartus II Chip Planner.
If you plan to migrate your design between Stratix® V GX A5, A7, A9, AB, B9, BB, D6, and D8 devices with 48 transceiver channels, and your design requires a PLL to drive the HSSI and clock network (GCLK or RCLK) simultaneously, use the 2 middle PLLs on the left or right side of the device.
|Variant||Member Code||Middle PLL Location|
|Left Side||Right Side|
|Stratix® V GX||A5||FRACTIONALPLL_X0_Y53, FRACTIONALPLL_X0_Y66||FRACTIONALPLL_X210_Y53, FRACTIONALPLL_X210_Y66|
|A9||FRACTIONALPLL_X0_Y77, FRACTIONALPLL_X0_Y86||FRACTIONALPLL_X225_Y77, FRACTIONALPLL_X225_Y86|
|D6||FRACTIONALPLL_X0_Y65, FRACTIONALPLL_X0_Y78||FRACTIONALPLL_X208_Y65, FRACTIONALPLL_X208_Y78|
You can configure the fractional PLL to function either in the integer or in the enhanced fractional mode. One fractional PLL can use up to 18 output counters and all external clock outputs. Two adjacent fractional PLLs share the 18 output counters.
Fractional PLLs can be used as follows:
- Reduce the number of required oscillators on the board
- Reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source
- Compensate clock network delay
- Zero delay buffering
- Transmit clocking for transceivers
Stratix® V devices support two types of PLL cascading.
This cascading mode synthesizes a more precise output frequency than a single PLL in integer mode. Cascading two PLLs in integer mode expands the effective range of the pre-scale counter, N and the multiply counter, M.
Stratix® V devices use two types of input clock sources.
- The adjpllin input clock source is used for inter-cascading between fracturable fractional PLLs.
- The cclk input clock source is used for intra-cascading within fracturable fractional PLLs.
Altera recommends using a low bandwidth setting for the source (upstream) PLL and a high bandwidth setting for destination (downstream) PLL.
This cascading mode synthesizes a lower frequency output than a single post-scale counter, C. Cascading two C counters expands the effective range of C counters.
Two adjacent corner and center fractional PLLs share four dual-purpose clock I/O pins, organized as one of the following combinations:
- Four single-ended clock outputs
- Two single-ended outputs and one differential clock output
- Four single-ended clock outputs and two single-ended feedback inputs in the I/O driver feedback for zero delay buffer (ZDB) mode support
- Two single-ended clock outputs and two single-ended feedback inputs for single-ended external feedback (EFB) mode support
- One differential clock output and one differential feedback input for differential EFB support (only one of the two adjacent fractional PLLs can support differential EFB at one time while the other fractional PLL can be used for general-purpose clocking)
The following figure shows that any of the output counters (C[0..17] ) or the M counter on the PLLs can feed the dedicated external clock outputs. Therefore, one counter or frequency can drive all output pins available from a given PLL.
Each pin of a single-ended output pair can be either in-phase or 180° out-of-phase. To implement the 180° out-of-phase pin in a pin pair, the Quartus® Prime software places a NOT gate in the design into the IOE.
The clock output pin pairs support the following I/O standards:
- Same I/O standard for the pin pairs
- Differential high-speed transceiver logic (HSTL)
- Differential SSTL
Stratix® V PLLs can drive out to any regular I/O pin through the GCLK or RCLK network. You can also use the external clock output pins as user I/O pins if you do not require external PLL clocking.
You can use the areset signal to control PLL operation and resynchronization, and use the locked signal to observe the status of the PLL.
The areset signal is the reset or resynchronization input for each PLL. The device input pins or internal logic can drive these input signals.
When areset is driven high, the PLL counters reset, clearing the PLL output and placing the PLL out-of-lock. The VCO is then set back to its nominal setting. When areset is driven low again, the PLL resynchronizes to its input as it re-locks.
You must assert the areset signal every time the PLL loses lock to guarantee the correct phase relationship between the PLL input and output clocks. You can set up the PLL to automatically reset (self-reset) after a loss-of-lock condition using the Quartus® Prime IP Catalog.
You must include the areset signal if either of the following conditions is true:
- PLL reconfiguration or clock switchover is enabled in the design
- Phase relationships between the PLL input and output clocks must be maintained after a loss-of-lock condition
The locked signal output of the PLL indicates the following conditions:
- The PLL has locked onto the reference clock.
- The PLL clock outputs are operating at the desired phase and frequency set in the IP Catalog.
The lock detection circuit provides a signal to the core logic. The signal indicates when the feedback clock has locked onto the reference clock both in phase and frequency.
This section describes the following clock feedback modes:
- Source synchronous
- LVDS compensation
- Normal compensation
Each mode allows clock multiplication and division, phase shifting, and programmable duty cycle.
The input and output delays are fully compensated by a PLL only when using the dedicated clock input pins associated with a given PLL as the clock source.
The input and output delays may not be fully compensated in the Quartus® Prime software for the following conditions:
- When a GCLK or RCLK network drives the PLL
- When the PLL is driven by a dedicated clock pin that is not associated with the PLL
For example, when you configure a PLL in ZDB mode, the PLL input is driven by an associated dedicated clock input pin. In this configuration, a fully compensated clock path results in zero delay between the clock input and one of the clock outputs from the PLL. However, if the PLL input is fed by a non-dedicated input (using the GCLK network), the output clock may not be perfectly aligned with the input clock.
If the data and clock arrive at the same time on the input pins, the same phase relationship is maintained at the clock and data ports of any IOE input register. Data and clock signals at the IOE experience similar buffer delays as long as you use the same I/O standard.
Altera recommends source synchronous mode for source synchronous data transfers.
The source synchronous mode compensates for the delay of the clock network used and any difference in the delay between the following two paths:
- Data pin to the IOE register input
- Clock input pin to the PLL phase frequency detector (PFD) input
The Stratix® V PLL can compensate multiple pad-to-input-register paths, such as a data bus when it is set to use source synchronous compensation mode.
The purpose of LVDS compensation mode is to maintain the same data and clock timing relationship seen at the pins of the internal serializer/deserializer (SERDES) capture register, except that the clock is inverted (180° phase shift). Thus, LVDS compensation mode ideally compensates for the delay of the LVDS clock network, including the difference in delay between the following two paths:
- Data pin-to-SERDES capture register
- Clock input pin-to-SERDES capture register
The output counter must provide the 180° phase shift.
In direct mode, the PLL does not compensate for any clock networks. This mode provides better jitter performance because the clock feedback into the PFD passes through less circuitry. Both the PLL internal- and external-clock outputs are phase-shifted with respect to the PLL clock input.
An internal clock in normal compensation mode is phase-aligned to the input clock pin. The external clock output pin has a phase delay relative to the clock input pin if connected in this mode. The Quartus® Prime TimeQuest Timing Analyzer reports any phase difference between the two. In normal compensation mode, the delay introduced by the GCLK or RCLK network is fully compensated.
In ZDB mode, the external clock output pin is phase-aligned with the clock input pin for zero delay through the device. This mode is supported only on the center and corner PLLs in Stratix® V devices.
When using this mode, you must use the same I/O standard on the input clocks and clock outputs to guarantee clock alignment at the input and output pins. You cannot use differential I/O standards on the PLL clock input or output pins.
To ensure phase alignment between the clk pin and the external clock output (CLKOUT) pin in ZDB mode, instantiate a bidirectional I/O pin in the design. The bidirectional I/O pin serves as the feedback path connecting the fbout and fbin ports of the PLL. The bidirectional I/O pin must always be assigned a single-ended I/O standard. The PLL uses this bidirectional I/O pin to mimic and compensate for the output delay from the clock output port of the PLL to the external clock output pin.
In EFB mode, the output of the M counter (fbout) feeds back to the PLL fbin input (using a trace on the board) and becomes part of the feedback loop.
One of the dual-purpose external clock outputs becomes the fbin input pin in this mode. The external feedback input pin, fbin is phase-aligned with the clock input pin. Aligning these clocks allows you to remove clock delay and skew between devices.
When using EFB mode, you must use the same I/O standard on the input clock, feedback input, and clock outputs.
This mode is supported only on the center and corner fractional PLLs in Stratix® V devices.
Normal and source synchronous compensation feedback mode require GCLK or RCLK feedback path to achieve the required phase relationship. Source synchronous mode for LVDS compensation does not require the GCLK or RCLK feedback path.
The GCLK or RCLK network feedback paths are fewer than the PLLs available on the device. You cannot implement the compensation mode that requires GCLK or RCLK feedback path on all the PLLs available on the device simultaneously.
Consider the following guidelines when implementing normal compensation or source synchronous compensation mode on multiple PLLs for the device:
- You can implement normal compensation or source synchronous compensation mode on all the center PLLs simultaneously.
- The Stratix® V device has two middle PLLs on the left and right side of the device. All PLLs that reside on each side of the device can be divided equally into 2 groups as shown in the following figure.
From the PLL grouping example, the PLLs can be divided into 4 different sections (upper left, lower left, upper right, and lower right). The PLLs in each of these sections can be further divided into first and second group. The first group consists of the 2 corner PLLs and one middle PLL located in each section. The remaining PLLs in the same section are grouped into the second group. For each section, you can use up to 3 PLLs to implement source synchronous or normal compensation mode in the following combinations:
- Any of the 3 PLLs in the first group
- Any of the 2 PLLs in the first group and 1 PLL in the second group
|PLL Section||PLL Location|
|First Group||Second Group|
|Upper left||FRACTIONALPLL_X0_Y122, FRACTIONALPLL_X0_Y113, FRACTIONALPLL_X0_Y66||FRACTIONALPLL_X0_Y100, FRACTIONALPLL_X0_Y91, FRACTIONALPLL_X0_Y75|
|Lower left||FRACTIONALPLL_X0_Y53, FRACTIONALPLL_X0_Y10, FRACTIONALPLL_X0_Y1||FRACTIONALPLL_X0_Y44, FRACTIONALPLL_X0_Y29, FRACTIONALPLL_X0_Y20|
|Upper right||FRACTIONALPLL_X210_Y122, FRACTIONALPLL_X210_Y113, FRACTIONALPLL_X210_Y66||FRACTIONALPLL_X210_Y100, FRACTIONALPLL_X210_Y91, FRACTIONALPLL_X210_Y75|
|Lower right||FRACTIONALPLL_X210_Y53, FRACTIONALPLL_X210_Y10, FRACTIONALPLL_X210_Y1||FRACTIONALPLL_X210_Y44, FRACTIONALPLL_X210_Y29, FRACTIONALPLL_X210_Y20|
Each Stratix® V PLL provides clock synthesis for PLL output ports using the M/(N × C) scaling factors. The input clock is divided by a pre-scale factor, N, and is then multiplied by the M feedback factor. The control loop drives the VCO to match fin × (M/N).
The Quartus® Prime software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered into the ALTERA_PLL IP core.
VCO Post Divider
A VCO post divider is inserted after the VCO. When you enable the VCO post divider, the VCO post divider divides the VCO frequency by two. When the VCO post divider is bypassed, the VCO frequency goes to the output port without being divided by two.
Post-Scale Counter, C
Each output port has a unique post-scale counter, C, that divides down the output from the VCO post divider. For multiple PLL outputs with different frequencies, the VCO is set to the least common multiple of the output frequencies that meets its frequency specifications. For example, if the output frequencies required from one PLL are 33 and 66 MHz, the Quartus® Prime software sets the VCO to 660 MHz (the least common multiple of 33 and 66 MHz within the VCO range). Then the post-scale counters, C, scale down the VCO frequency for each output port.
Pre-Scale Counter, N and Multiply Counter, M
Each PLL has one pre-scale counter, N, and one multiply counter, M, with a range of 1 to 512 for both M and N. The N counter does not use duty-cycle control because the only purpose of this counter is to calculate frequency division. The post-scale counters have a 50% duty cycle setting. The high- and low-count values for each counter range from 1 to 256. The sum of the high- and low-count values chosen for a design selects the divide value for a given counter.
The delta-sigma modulator (DSM) is used together with the M multiply counter to enable the PLL to operate in fractional mode. The DSM dynamically changes the M counter divide value on a cycle to cycle basis. The different M counter values allow the "average" M counter value to be a non-integer.
In fractional mode, the M counter divide value equals to the sum of the "clock high" count, "clock low" count, and the fractional value. The fractional value is equal to K/2^X , where K is an integer between 0 and (2^X – 1), and X = 8, 16, 24, or 32.
For PLL operating in integer mode, M is an integer value and DSM is disabled.
The programmable phase shift feature allows the PLLs to generate output clocks with a fixed phase offset.
The VCO frequency of the PLL determines the precision of the phase shift. The minimum phase shift increment is 1/8 of the VCO period. For example, if a PLL operates with a VCO frequency of 1000 MHz, phase shift steps of 125 ps are possible.
The Quartus® Prime software automatically adjusts the VCO frequency according to the user-specified phase shift values entered into the IP core.
The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This feature is supported on the PLL post-scale counters.
The duty-cycle setting is achieved by a low and high time-count setting for the post-scale counters. To determine the duty cycle choices, the Quartus® Prime software uses the frequency input and the required multiply or divide rate.
The post-scale counter value determines the precision of the duty cycle. The precision is defined as 50% divided by the post-scale counter value. For example, if the C0 counter is 10, steps of 5% are possible for duty-cycle choices from 5% to 90%. If the PLL is in external feedback mode, set the duty cycle for the counter driving the fbin pin to 50%.
Combining the programmable duty cycle with programmable phase shift allows the generation of precise non-overlapping clocks.
The clock switchover feature allows the PLL to switch between two reference input clocks. Use this feature for clock redundancy or for a dual-clock domain application where a system turns on the redundant clock if the previous clock stops running. The design can perform clock switchover automatically when the clock is no longer toggling or based on a user control signal, clkswitch.
The following clock switchover modes are supported in Stratix® V PLLs:
- Automatic switchover—The clock sense circuit monitors the current reference clock. If the current reference clock stops toggling, the reference clock automatically switches to inclk0 or inclk1 clock.
- Manual clock switchover—Clock switchover is controlled using the clkswitch signal. When the clkswitch signal goes from logic low to logic high, and stays high for at least three clock cycles, the reference clock to the PLL is switched from inclk0 to inclk1, or vice-versa.
- Automatic switchover with manual override—This mode combines automatic switchover and manual clock switchover. When the clkswitch signal goes high, it overrides the automatic clock switchover function. As long as the clkswitch signal is high, further switchover action is blocked.
Stratix® V PLLs support a fully configurable clock switchover capability.
When the current reference clock is not present, the clock sense block automatically switches to the backup clock for PLL reference. You can select a clock source as the backup clock by connecting it to the inclk1 port of the PLL in your design.
The clock switchover circuit sends out three status signals—clkbad, clkbad, and activeclock—from the PLL to implement a custom switchover circuit in the logic array.
In automatic switchover mode, the clkbad and clkbad signals indicate the status of the two clock inputs. When they are asserted, the clock sense block detects that the corresponding clock input has stopped toggling. These two signals are not valid if the frequency difference between inclk0 and inclk1 is greater than 20%.
The activeclock signal indicates which of the two clock inputs (inclk0 or inclk1) is being selected as the reference clock to the PLL. When the frequency difference between the two clock inputs is more than 20%, the activeclock signal is the only valid status signal.
Use the switchover circuitry to automatically switch between inclk0 and inclk1 when the current reference clock to the PLL stops toggling. You can switch back and forth between inclk0 and inclk1 any number of times when one of the two clocks fails and the other clock is available.
For example, in applications that require a redundant clock with the same frequency as the reference clock, the switchover state machine generates a signal (clksw) that controls the multiplexer select input. In this case, inclk1 becomes the reference clock for the PLL.
When using automatic clock switchover mode, the following requirements must be satisfied:
- Both clock inputs must be running when the FPGA is configured.
- The period of the two clock inputs can differ by no more than 20%.
If the current clock input stops toggling while the other clock is also not toggling, switchover is not initiated and the clkbad[0..1] signals are not valid. If both clock inputs are not the same frequency, but their period difference is within 20%, the clock sense block detects when a clock stops toggling. However, the PLL may lose lock after the switchover is completed and needs time to relock.
In automatic switchover with manual override mode, you can use the clkswitch signal for user- or system-controlled switch conditions. You can use this mode for same-frequency switchover, or to switch between inputs of different frequencies.
For example, if inclk0 is 66 MHz and inclk1 is 200 MHz, you must control switchover using the clkswitch signal. The automatic clock-sense circuitry cannot monitor clock input (inclk0 and inclk1) frequencies with a frequency difference of more than 100% (2×).
This feature is useful when the clock sources originate from multiple cards on the backplane, requiring a system-controlled switchover between the frequencies of operation.
You must choose the backup clock frequency and set the M, N, C, and K counters so that the VCO operates within the recommended operating frequency range. The ALTERA_PLL IP Catalog notifies you if a given combination of inclk0 and inclk1 frequencies cannot meet this requirement.
In automatic override with manual switchover mode, the activeclock signal mirrors the clkswitch signal. Since both clocks are still functional during the manual switch, neither clkbad signal goes high. Because the switchover circuit is positive-edge sensitive, the falling edge of the clkswitch signal does not cause the circuit to switch back from inclk1 to inclk0. When the clkswitch signal goes high again, the process repeats.
The clkswitch signal and automatic switch work only if the clock being switched to is available. If the clock is not available, the state machine waits until the clock is available.
In manual clock switchover mode, the clkswitch signal controls whether inclk0 or inclk1 is selected as the input clock to the PLL. By default, inclk0 is selected.
A clock switchover event is initiated when the clkswitch signal transitions from logic low to logic high, and being held high for at least three inclk cycles.
You must bring the clkswitch signal back low again to perform another switchover event. If you do not require another switchover event, you can leave the clkswitch signal in a logic high state after the initial switch.
Pulsing the clkswitch signal high for at least three inclk cycles performs another switchover event.
If inclk0 and inclk1 are different frequencies and are always running, the clkswitchsignal minimum high time must be greater than or equal to three of the slower frequency inclk0 and inclk1 cycles.
You can delay the clock switchover action by specifying the switchover delay in the ALTERA_PLL IP core. When you specify the switchover delay, the clkswitch signal must be held high for at least three inclk cycles plus the number of the delay cycles that has been specified to initiate a clock switchover.
When implementing clock switchover in Stratix® V PLLs, use the following guidelines:
- Automatic clock switchover requires that the inclk0 and inclk1 frequencies be within 20% of each other. Failing to meet this requirement causes the clkbad and clkbad signals to not function properly.
- When using manual clock switchover, the difference between inclk0 and inclk1 can be more than 100% (2×). However, differences in frequency, phase, or both, of the two clock sources will likely cause the PLL to lose lock. Resetting the PLL ensures that you maintain the correct phase relationships between the input and output clocks.
- Both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate the manual clock switchover event. Failing to meet this requirement causes the clock switchover to not function properly.
- Applications that require a clock switchover feature and a small frequency drift must use a low-bandwidth PLL. When referencing input clock changes, the low-bandwidth PLL reacts more slowly than a high-bandwidth PLL. When switchover happens, a low-bandwidth PLL propagates the stopping of the clock to the output more slowly than a high-bandwidth PLL. However, be aware that the low-bandwidth PLL also increases lock time.
- After a switchover occurs, there may be a finite resynchronization period for the PLL to lock onto a new clock. The time it takes for the PLL to relock depends on the PLL configuration.
- The phase relationship between the input clock to the PLL and the output clock from the PLL is important in your design. Assert areset for at least 10 ns after performing a clock switchover. Wait for the locked signal to go high and be stable before re-enabling the output clocks from the PLL.
- The VCO frequency gradually decreases when the current clock is lost and then increases as the VCO locks on to the backup clock, as shown in the following figure.
For more information about PLL reconfiguration and dynamic phase shifting, refer to AN661.
|December 2016||2016.12.09||Added a note to dedicated refclk pin in Fractional PLL High-Level Block Diagram.|
|December 2015||2015.12.21||Changed instances of Quartus II to Quartus Prime.|
|November 2011||1.3||Updated Figure 4–19 and Figure 4–28.|
|December 2010||1.1||No changes to the content of this chapter for the Quartus II software 10.1.|
|July 2010||1.0||Initial release.|
This chapter provides details about the features of the Stratix® V I/O elements (IOEs) and how the IOEs work in compliance with current and emerging I/O standards and requirements.
The Stratix® V I/Os support the following features:
- True LVDS channels in all I/O banks support SGMII, SPI-4.2, and XSBI applications
- Hard dynamic phase alignment (DPA) and serializer/deserializer (SERDES) support in I/O banks on all sides of the device with DPA
- Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
- Low-voltage differential signaling (LVDS), RSDS, mini-LVDS, HSTL, HSUL, and SSTL I/O standards across all I/O banks
- Double data rate (DDR), single data rate (SDR), and half data rate input and output options
- Serializer/deserializer (SERDES)
- Deskew, read and write leveling, and clock-domain crossing functionality for high-performance memory interface
- Programmable output current strength
- Programmable slew-rate
- Programmable bus-hold
- Programmable pull-up resistor
- Programmable pre-emphasis
- Programmable I/O delay
- Programmable voltage output differential (VOD)
- Open-drain output
- On-chip series termination (RS OCT) with and without calibration
- On-chip parallel termination (RT OCT)
- On-chip differential termination (RD OCT)
This section lists the I/O standards supported in the FPGA I/Os of Stratix® V devices, the typical power supply values for each I/O standard, and the MultiVolt I/O interface feature.
Stratix® V devices support a wide range of industry I/O standards. These devices support VCCIO voltage levels of 3.0, 2.5, 1.8, 1.5, 1.35, 1.25, and 1.2 V.
|I/O Standard||Typical Applications||Standard Support|
|3.3 V LVTTL/3.3 V LVCMOS4||General purpose||JESD8-B|
|2.5 V LVCMOS||General purpose||JESD8-5|
|1.8 V LVCMOS||General purpose||JESD8-7|
|1.5 V LVCMOS||General purpose||JESD8-11|
|1.2 V LVCMOS||General purpose||JESD8-12|
|SSTL-2 Class I||DDR SDRAM||JESD8-9B|
|SSTL-2 Class II||DDR SDRAM||JESD8-9B|
|SSTL-18 Class I||DDR2 SDRAM||JESD8-15|
|SSTL-18 Class II||DDR2 SDRAM||JESD8-15|
|SSTL-15 Class I||DDR3 SDRAM||—|
|SSTL-15 Class II||DDR3 SDRAM||—|
|1.8 V HSTL Class I||QDR II/RLDRAM II||JESD8-6|
|1.8 V HSTL Class II||QDR II/RLDRAM II||JESD8-6|
|1.5 V HSTL Class I||QDR II/QDR II+/RLDRAM II||JESD8-6|
|1.5 V HSTL Class II||QDR II/QDR II+/RLDRAM II||JESD8-6|
|1.2 V HSTL Class I||General purpose||JESD8-16A|
|1.2 V HSTL Class II||General purpose||JESD8-16A|
|Differential SSTL-2 Class I||DDR SDRAM||JESD8-9B|
|Differential SSTL-2 Class II||DDR SDRAM||JESD8-9B|
|Differential SSTL-18 Class I||DDR2 SDRAM||JESD8-15|
|Differential SSTL-18 Class II||DDR2 SDRAM||JESD8-15|
|Differential SSTL-15 Class I||DDR3 SDRAM||—|
|Differential SSTL-15 Class II||DDR3 SDRAM||—|
|Differential 1.8 V HSTL Class I||Clock interfaces||JESD8-6|
|Differential 1.8 V HSTL Class II||Clock interfaces||JESD8-6|
|Differential 1.5 V HSTL Class I||Clock interfaces||JESD8-6|
|Differential 1.5 V HSTL Class II||Clock interfaces||JESD8-6|
|Differential 1.2 V HSTL Class I||Clock interfaces||JESD8-16A|
|Differential 1.2 V HSTL Class II||Clock interfaces||JESD8-16A|
|RSDS||Flat panel display||—|
|Mini-LVDS||Flat panel display||—|
|LVPECL||Video graphics and clock distribution||—|
|Differential SSTL-15||DDR3 SDRAM||JESD79-3D|
|Differential SSTL-135||DDR3L SDRAM||—|
|Differential SSTL-125||DDR3U SDRAM||—|
|Differential SSTL-12||RLDRAM 3||—|
|Differential HSUL-12||LPDDR2 SDRAM||—|
|I/O Standard||VCCIO (V)||
(Input Ref Voltage)
(Board Termination Voltage)
|3.3 V LVTTL/3.3 V LVCMOS||3.0/2.5||3.0||3.0||—||—|
|2.5 V LVCMOS||3.0/2.5||2.5||2.5||—||—|
|1.8 V LVCMOS||1.8/1.5||1.8||2.5||—||—|
|1.5 V LVCMOS||1.8/1.5||1.5||2.5||—||—|
|1.2 V LVCMOS||1.2||1.2||2.5||—||—|
|SSTL-2 Class I||VCCPD||2.5||2.5||1.25||1.25|
|SSTL-2 Class II||VCCPD||2.5||2.5||1.25||1.25|
|SSTL-18 Class I||VCCPD||1.8||2.5||0.9||0.9|
|SSTL-18 Class II||VCCPD||1.8||2.5||0.9||0.9|
|SSTL-15 Class I||VCCPD||1.5||2.5||0.75||0.75|
|SSTL-15 Class II||VCCPD||1.5||2.5||0.75||0.75|
|1.8 V HSTL Class I||VCCPD||1.8||2.5||0.9||0.9|
|1.8 V HSTL Class II||VCCPD||1.8||2.5||0.9||0.9|
|1.5 V HSTL Class I||VCCPD||1.5||2.5||0.75||0.75|
|1.5 V HSTL Class II||VCCPD||1.5||2.5||0.75||0.75|
|1.2 V HSTL Class I||VCCPD||1.2||2.5||0.6||0.6|
|1.2 V HSTL Class II||VCCPD||1.2||2.5||0.6||0.6|
|Differential SSTL-2 Class I||VCCPD||2.5||2.5||—||1.25|
|Differential SSTL-2 Class II||VCCPD||2.5||2.5||—||1.25|
|Differential SSTL-18 Class I||VCCPD||1.8||2.5||—||0.9|
|Differential SSTL-18 Class II||VCCPD||1.8||2.5||—||0.9|
|Differential SSTL-15 Class I||VCCPD||1.5||2.5||—||0.75|
|Differential SSTL-15 Class II||VCCPD||1.5||2.5||—||0.75|
|Differential 1.8 V HSTL Class I||VCCPD||1.8||2.5||—||0.9|
|Differential 1.8 V HSTL Class II||VCCPD||1.8||2.5||—||0.9|
|Differential 1.5 V HSTL Class I||VCCPD||1.5||2.5||—||0.75|
|Differential 1.5 V HSTL Class II||VCCPD||1.5||2.5||—||0.75|
|Differential 1.2 V HSTL Class I||VCCPD||1.2||2.5||—||0.6|
|Differential 1.2 V HSTL Class II||VCCPD||1.2||2.5||—||0.6|
|LVPECL (Differential clock input only)||VCCPD||—||2.5||—||—|
|SSTL-15||VCCPD||1.5||2.5||0.75||Typically does not require board termination|
|Differential SSTL-15||VCCPD||1.5||2.5||—||Typically does not require board termination|