Intel^® Arria^® 10 device family delivers:

• Higher performance than the previous generation of mid-range and high-end FPGAs.
• Power efficiency attained through a comprehensive set of power-saving technologies.

The Intel^® Arria^® 10 devices are ideal for high performance, power-sensitive, midrange applications in diverse markets.

This section provides the available options, maximum resource counts, and package plan for the Intel^® Arria^® 10 GX devices.

The information in this section is correct at the time of publication. For the latest information and to get more details, refer to the Intel FPGA Product Selector.

This section provides the available options, maximum resource counts, and package plan for the Intel^® Arria^® 10 GT devices.

The information in this section is correct at the time of publication. For the latest information and to get more details, refer to the Intel FPGA Product Selector.

This section provides the available options, maximum resource counts, and package plan for the Intel^® Arria^® 10 SX devices.

The information in this section is correct at the time of publication. For the latest information and to get more details, refer to the Intel FPGA Product Selector.

Intel^® Arria^® 10 devices use a 20 nm ALM as the basic building block of the logic fabric.

The ALM architecture is the same as the previous generation FPGAs, allowing for efficient implementation of logic functions and easy conversion of IP between the device generations.

The ALM, as shown in following figure, uses an 8-input fracturable look-up table (LUT) with four dedicated registers to help improve timing closure in register-rich designs and achieve an even higher design packing capability than the traditional two-register per LUT architecture.

The Intel^® Quartus^® Prime software optimizes your design according to the ALM logic structure and automatically maps legacy designs into the Intel^® Arria^® 10 ALM architecture.

The embedded memory blocks in the devices are flexible and designed to provide an optimal amount of small- and large-sized memory arrays to fit your design requirements.

The Intel^® Arria^® 10 devices contain two types of memory blocks:

• 20 Kb M20K blocks—blocks of dedicated memory resources. The M20K blocks are ideal for larger memory arrays while still providing a large number of independent ports.
• 640 bit memory logic array blocks (MLABs)—enhanced memory blocks that are configured from dual-purpose logic array blocks (LABs). The MLABs are ideal for wide and shallow memory arrays. The MLABs are optimized for implementation of shift registers for digital signal processing (DSP) applications, wide and shallow FIFO buffers, and filter delay lines. Each MLAB is made up of ten adaptive logic modules (ALMs). In the Intel^® Arria^® 10 devices, you can configure these ALMs as ten 32 x 2 blocks, giving you one 32 x 20 simple dual-port SRAM block per MLAB.

To reduce power consumption, the Intel^® Quartus^® Prime software identifies all unused sections of the clock network and powers them down.

Intel^® Arria^® 10 devices contain up to 32 fractional synthesis PLLs and up to 16 I/O PLLs that are available for both specific and general purpose uses in the core:

• Fractional synthesis PLLs—located in the column adjacent to the transceiver blocks
• I/O PLLs—located in each bank of the 48 I/Os

You can use the fractional synthesis PLLs to:

• Reduce the number of oscillators that are required on your board
• Reduce the number of clock pins that are used in the device by synthesizing multiple clock frequencies from a single reference clock source

The fractional synthesis PLLs support the following features:

• Reference clock frequency synthesis for transceiver CMU and Advanced Transmit (ATX) PLLs
• Clock network delay compensation
• Zero-delay buffering
• Direct transmit clocking for transceivers
• Independently configurable into two modes:
  • Conventional integer mode equivalent to the general purpose PLL
  • Enhanced fractional mode with third order delta-sigma modulation
• PLL cascading

In each I/O bank, the I/O PLLs are adjacent to the hard memory controllers and LVDS SERDES. Because these PLLs are tightly coupled with the I/Os that need to use them, it makes it easier to close timing.

You can use the I/O PLLs for general purpose applications in the core such as clock network delay compensation and zero-delay buffering.

Intel^® Arria^® 10 devices support PLL-to-PLL cascading.

Intel^® Arria^® 10 devices offer highly configurable GPIOs. Each I/O bank contains 48 general purpose I/Os and a high-efficiency hard memory controller.

The following list describes the features of the GPIOs:

• Consist of 3 V I/Os for high-voltage application and LVDS I/Os for differential signaling
  • Up to two 3 V I/O banks, available in some devices, that support up to 3 V I/O standards
  • LVDS I/O banks that support up to 1.8 V I/O standards
• Support a wide range of single-ended and differential I/O interfaces
• LVDS speeds up to 1.6 Gbps
• Each LVDS pair of pins has differential input and output buffers, allowing you to configure the LVDS direction for each pair.
• Programmable bus hold and weak pull-up
• Programmable differential output voltage (V_OD) and programmable pre-emphasis
• Series (R_S ) and parallel (R_T ) on-chip termination (OCT) for all I/O banks with OCT calibration to limit the termination impedance variation
• On-chip dynamic termination that has the ability to swap between series and parallel termination, depending on whether there is read or write on a common bus for signal integrity
• Easy timing closure support using the hard read FIFO in the input register path, and delay-locked loop (DLL) delay chain with fine and coarse architecture

The memory interface within Intel^® Arria^® 10 FPGAs and SoCs delivers the highest performance and ease of use. You can configure up to a maximum width of 144 bits when using the hard or soft memory controllers. If required, you can bypass the hard memory controller and use a soft controller implemented in the user logic.

Each I/O contains a hardened DDR read/write path (PHY) capable of performing key memory interface functionality such as read/write leveling, FIFO buffering to lower latency and improve margin, timing calibration, and on-chip termination.

The timing calibration is aided by the inclusion of hard microcontrollers based on Intel's Nios^® II technology, specifically tailored to control the calibration of multiple memory interfaces. This calibration allows the Intel^® Arria^® 10 device to compensate for any changes in process, voltage, or temperature either within the Intel^® Arria^® 10 device itself, or within the external memory device. The advanced calibration algorithms ensure maximum bandwidth and robust timing margin across all operating conditions.

In addition to parallel memory interfaces, Intel^® Arria^® 10 devices support serial memory technologies such as the Hybrid Memory Cube (HMC). The HMC is supported by the Intel^® Arria^® 10 high-speed serial transceivers which connect up to four HMC links, with each link running at data rates up to 15 Gbps.

Intel^® Arria^® 10 devices contain PCIe hard IP that is designed for performance and ease-of-use:

• Includes all layers of the PCIe stack—transaction, data link and physical layers.
• Supports PCIe Gen3, Gen2, and Gen1 Endpoint and Root Port in x1, x2, x4, or x8 lane configuration.
• Operates independently from the core logic—optional configuration via protocol (CvP) allows the PCIe link to power up and complete link training in less than 100 ms while the Intel^® Arria^® 10 device completes loading the programming file for the rest of the FPGA.
• Provides added functionality that makes it easier to support emerging features such as Single Root I/O Virtualization (SR-IOV) and optional protocol extensions.
• Provides improved end-to-end datapath protection using ECC.
• Supports FPGA configuration via protocol (CvP) using PCIe at Gen3, Gen2, or Gen1 speed.

The Interlaken PCS is based on the proven functionality of the PCS developed for Intel’s previous generation FPGAs, which demonstrated interoperability with Interlaken ASSP vendors and third-party IP suppliers. The Interlaken PCS is present in every transceiver channel in Intel^® Arria^® 10 devices.

The scalable hard IP supports multiple independent 10GbE ports while using a single PLL for all the 10GBASE-R PCS instantiations, which saves on core logic resources and clock networks:

• Simplifies multiport 10GbE systems compared to XAUI interfaces that require an external XAUI-to-10G PHY.
• Incorporates Electronic Dispersion Compensation (EDC), which enables direct connection to standard 10 Gbps XFP and SFP+ pluggable optical modules.
• Supports backplane Ethernet applications and includes a hard 10GBASE-KR Forward Error Correction (FEC) circuit that you can use for 10 Gbps and 40 Gbps applications.

The 10 Gbps Ethernet PCS hard IP and 10GBASE-KR FEC are present in every transceiver channel.

Intel^® Arria^® 10 devices deliver the industry's lowest power consumption per transceiver channel:

• 12.5 Gbps transceivers at as low as 242 mW
• 10 Gbps transceivers at as low as 168 mW
• 6 Gbps transceivers at as low as 117 mW

Intel^® Arria^® 10 transceivers support various data rates according to application:

• Chip-to-chip and chip-to-module applications—from 1 Gbps up to 25.8 Gbps
• Long reach and backplane applications—from 1 Gbps up to 12.5 with advanced adaptive equalization
• Critical power sensitive applications—from 1 Gbps up to 11.3 Gbps using lower power modes

The combination of 20 nm process technology and architectural advances provide the following benefits:

• Significant reduction in die area and power consumption
• Increase of up to two times in transceiver I/O density compared to previous generation devices while maintaining optimal signal integrity
• Up to 72 total transceiver channels—you can configure up to 6 of these channels to run as fast as 25.8 Gbps
• All channels feature continuous data rate support up to the maximum rated speed

• The PMA provides primary interfacing capabilities to physical channels.
• The PCS typically handles encoding/decoding, word alignment, and other pre-processing functions before transferring data to the FPGA core fabric.

A transceiver channel consists of a PMA and a PCS block. Most transceiver banks have 6 channels. There are some transceiver banks that contain only 3 channels.

A wide variety of bonded and non-bonded data rate configurations is possible using a highly configurable clock distribution network. Up to 80 independent transceiver data rates can be configured.

The following figures are graphical representations of top views of the silicon die, which correspond to reverse views for flip chip packages. Different Intel^® Arria^® 10 devices may have different floorplans than the ones shown in the figures.

Intel^® Arria^® 10 transceivers provide exceptional signal integrity at data rates up to 25.8 Gbps. Clocking options include ultra-low jitter ATX PLLs (LC tank based), clock multiplier unit (CMU) PLLs, and fractional PLLs.

Each transceiver channel contains a channel PLL that can be used as the CMU PLL or clock data recovery (CDR) PLL. In CDR mode, the channel PLL recovers the receiver clock and data in the transceiver channel. Up to 80 independent data rates can be configured on a single Intel^® Arria^® 10 device.

This table summarizes the Intel^® Arria^® 10 transceiver PCS features. You can use the transceiver PCS to support a wide range of protocols ranging from 1 Gbps to 25.8 Gbps.

This table lists some of the protocols supported by the Intel^® Arria^® 10 transceiver PCS. For more information about the blocks in the transmitter and receiver data paths, refer to the related information.

Each SoC device combines an FPGA fabric and a hard processor system (HPS) in a single device. This combination delivers the flexibility of programmable logic with the power and cost savings of hard IP in these ways:

• Reduces board space, system power, and bill of materials cost by eliminating a discrete embedded processor
• Allows you to differentiate the end product in both hardware and software, and to support virtually any interface standard
• Extends the product life and revenue through in-field hardware and software updates

The 20-nm HPS strikes a balance between enabling maximum software compatibility with 28-nm SoCs while still improving upon the 28-nm HPS architecture. These improvements address the requirements of the next generation target markets such as wireless and wireline communications, compute and storage equipment, broadcast and military in terms of performance, memory bandwidth, connectivity via backplane and security.

The HPS has the following features:

• 1.2-GHz, dual-core ARM Cortex-A9 MPCore processor with up to 1.5-GHz via overdrive
  • ARMv7-A architecture that runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java byte codes in Jazelle style
  • Superscalar, variable length, out-of-order pipeline with dynamic branch prediction
  • Instruction Efficiency 2.5 MIPS/MHz, which provides total performance of 7500 MIPS at 1.5 GHz
• Each processor core includes:
  • 32 KB of L1 instruction cache, 32 KB of L1 data cache
  • Single- and double-precision floating-point unit and NEON media engine
  • CoreSight debug and trace technology
  • Snoop Control Unit (SCU) and Acceleration Coherency Port (ACP)
• 512 KB of shared L2 cache
• 256 KB of scratch RAM
• Hard memory controller with support for DDR3, DDR4 and optional error correction code (ECC) support
• Multiport Front End (MPFE) Scheduler interface to the hard memory controller 
• 8-channel direct memory access (DMA) controller
• QSPI flash controller with SIO, DIO, QIO SPI Flash support
• NAND flash controller (ONFI 1.0 or later) with DMA and ECC support, updated to support 8 and 16-bit Flash devices and new command DMA to offload CPU for fast power down recovery
• Updated SD/SDIO/MMC controller to eMMC 4.5 with DMA with CE-ATA digital command support
• 3 10/100/1000 Ethernet media access control (MAC) with DMA
• 2 USB On-the-Go (OTG) controllers with DMA
• 5 I²C controllers (3 can be used by EMAC for MIO to external PHY)
• 2 UART 16550 Compatible controllers
• 4 serial peripheral interfaces (SPI) (2 Master, 2 Slaves)
• 62 programmable general-purpose I/Os, which includes 48 direct share I/Os that allows the HPS peripherals to connect directly to the FPGA I/Os
• 7 general-purpose timers
• 4 watchdog timers
• Anti-tamper, Secure Boot, Encryption (AES) and Authentication (SHA)

Each Ethernet MAC, USB OTG, NAND flash controller, and SD/MMC controller module has an integrated DMA controller. For modules without an integrated DMA controller, an additional DMA controller module provides up to eight channels of high-bandwidth data transfers. Peripherals that communicate off-chip are multiplexed with other peripherals at the HPS pin level. This allows you to choose which peripherals interface with other devices on your PCB.

The debug access port provides interfaces to industry standard JTAG debug probes and supports ARM CoreSight debug and core traces to facilitate software development.

The HPS–FPGA bridges, which support the Advanced Microcontroller Bus Architecture (AMBA^®) Advanced eXtensible Interface (AXI™) specifications, consist of the following bridges:

• FPGA-to-HPS AMBA AXI bridge—a high-performance bus supporting 32, 64, and 128 bit data widths that allows the FPGA fabric to issue transactions to slaves in the HPS.
• HPS-to-FPGA Avalon/AMBA AXI bridge—a high-performance bus supporting 32, 64, and 128 bit data widths that allows the HPS to issue transactions to slaves in the FPGA fabric.
• Lightweight HPS-to-FPGA AXI bridge—a lower latency 32 bit width bus that allows the HPS to issue transactions to soft peripherals in the FPGA fabric. This bridge is primarily used for control and status register (CSR) accesses to peripherals in the FPGA fabric.

The HPS–FPGA AXI bridges allow masters in the FPGA fabric to communicate with slaves in the HPS logic, and vice versa. For example, the HPS-to-FPGA AXI bridge allows you to share memories instantiated in the FPGA fabric with one or both microprocessors in the HPS, while the FPGA-to-HPS AXI bridge allows logic in the FPGA fabric to access the memory and peripherals in the HPS.

Each HPS–FPGA bridge also provides asynchronous clock crossing for data transferred between the FPGA fabric and the HPS.

The HPS SDRAM controller subsystem contains a multiport SDRAM controller and DDR PHY that are shared between the FPGA fabric (through the FPGA-to-HPS SDRAM interface), the level 2 (L2) cache, and the level 3 (L3) system interconnect. The FPGA-to-HPS SDRAM interface supports AMBA AXI and Avalon^® Memory-Mapped (Avalon-MM) interface standards, and provides up to six individual ports for access by masters implemented in the FPGA fabric.

The HPS SDRAM controller supports up to 3 masters (command ports), 3x 64-bit read data ports and 3x 64-bit write data ports.

To maximize memory performance, the SDRAM controller subsystem supports command and data reordering, deficit round-robin arbitration with aging, and high-priority bypass features.

The FPGA fabric and HPS in the SoC FPGA must be powered at the same time. You can reduce the clock frequencies or gate the clocks to reduce dynamic power.

Once powered, the FPGA fabric and HPS can be configured independently thus providing you with more design flexibility:

• You can boot the HPS independently. After the HPS is running, the HPS can fully or partially reconfigure the FPGA fabric at any time under software control. The HPS can also configure other FPGAs on the board through the FPGA configuration controller.
• Configure the FPGA fabric first, and then boot the HPS from memory accessible to the FPGA fabric.

For hardware development, you can configure the HPS and connect your soft logic in the FPGA fabric to the HPS interfaces using the Platform Designer system integration tool in the Intel^® Quartus^® Prime software.

For software development, the ARM-based SoC FPGA devices inherit the rich software development ecosystem available for the ARM Cortex-A9 MPCore processor. The software development process for Intel SoC FPGAs follows the same steps as those for other SoC devices from other manufacturers. Support for Linux^®, VxWorks^®, and other operating systems are available for the SoC FPGAs. For more information on the operating systems support availability, contact the Intel FPGA sales team.

You can begin device-specific firmware and software development on the Intel SoC FPGA Virtual Target. The Virtual Target is a fast PC-based functional simulation of a target development system—a model of a complete development board. The Virtual Target enables the development of device-specific production software that can run unmodified on actual hardware.

The Intel^® Arria^® 10 devices support dynamic and partial reconfiguration. You can use dynamic and partial reconfiguration simultaneously to enable seamless reconfiguration of both the device core and transceivers.

You can reconfigure the PMA and PCS blocks while the device continues to operate. This feature allows you to change the data rates, protocol, and analog settings of a channel in a transceiver bank without affecting on-going data transfer in other transceiver banks. This feature is ideal for applications that require dynamic multiprotocol or multirate support.

Using partial reconfiguration, you can reconfigure some parts of the device while keeping the device in operation.

Instead of placing all device functions in the FPGA fabric, you can store some functions that do not run simultaneously in external memory and load them only when required. This capability increases the effective logic density of the device, and lowers cost and power consumption.

In the Intel^® solution, you do not have to worry about intricate device architecture to perform a partial reconfiguration. The partial reconfiguration capability is built into the Intel^® Quartus^® Prime design software, making such time-intensive task simple.

Intel^® Arria^® 10 devices support partial reconfiguration in the following configuration options:

• Using an internal host:

  • All supported configuration modes where the FPGA has access to external memory devices such as serial and parallel flash memory.

  • Configuration via Protocol [CvP (PCIe)]
• Using an external host—passive serial (PS), fast passive parallel (FPP) x8, FPP x16, and FPP x32 I/O interface.

You can configure Intel^® Arria^® 10 devices through PCIe using Configuration via Protocol (CvP). The Intel^® Arria^® 10 CvP implementation conforms to the PCIe 100 ms power-up-to-active time requirement.

The detection and correction circuitry includes protection for Configuration RAM (CRAM) programming bits and user memories. The CRAM is protected by a continuously running CRC error detection circuit with integrated ECC that automatically corrects one or two errors and detects higher order multi-bit errors. When more than two errors occur, correction is available through reloading of the core programming file, providing a complete design refresh while the FPGA continues to operate.

The physical layout of the Intel^® Arria^® 10 CRAM array is optimized to make the majority of multi-bit upsets appear as independent single-bit or double-bit errors which are automatically corrected by the integrated CRAM ECC circuitry. In addition to the CRAM protection, the M20K memory blocks also include integrated ECC circuitry and are layout-optimized for error detection and correction. The MLAB does not have ECC.

The optional power reduction techniques in Intel^® Arria^® 10 devices include:

• SmartVID—a code is programmed into each device during manufacturing that allows a smart regulator to operate the device at lower core V_CC while maintaining performance
• Programmable Power Technology—non-critical timing paths are identified by the Intel^® Quartus^® Prime software and the logic in these paths is biased for low power instead of high performance
• Low Static Power Options—devices are available with either standard static power or low static power while maintaining performance

Furthermore, Intel^® Arria^® 10 devices feature Intel’s industry-leading low power transceivers and include a number of hard IP blocks that not only reduce logic resources but also deliver substantial power savings compared to soft implementations. In general, hard IP blocks consume up to 90% less power than the equivalent soft logic implementations.

Incremental compilation supports top-down, bottom-up, and team-based design flows. This feature facilitates modular, hierarchical, and team-based design flows where different designers compile their respective design sections in parallel. Furthermore, different designers or IP providers can develop and optimize different blocks of the design independently. These blocks can then be imported into the top level project.