The Intel® FPGA OCT IP core allows you to dynamically calibrate I/O with reference to an external resistor. The Intel® FPGA OCT IP core improves signal integrity, reduces board space, and is necessary for communicating with external devices such as memory interfaces.
The Intel® FPGA OCT IP core is available for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices only. For Stratix® V, Arria® V, and Cyclone® V devices, you need to migrate the IP core. For more details, refer to the related information.
The Intel® FPGA OCT IP core supports the following features:
- Support for up to 12 on-chip termination (OCT) blocks
- Support for calibrated on-chip series termination (RS) and calibrated on-chip parallel termination (RT) on all I/O pins
- Calibrated termination values of 25 Ω and 50 Ω
- Support for OCT calibration in power-up and user modes
|OCT block||Generates and sends calibration code words to the I/O buffer blocks.|
|OCT logic||Receives the calibration code words serially from the OCT block and sends the calibration code words in parallel to the buffers.|
- RZQ pins are dual-purpose pins. If the pins are not connected to the OCT block, you can use the pins as regular I/O pins.
- Calibrated pins must have the same VCCIO voltage as the OCT block and the RZQ pin. Calibrated pins connected to the same OCT block must have the same series and parallel termination values.
- You can apply location constraints on the RZQ pins to determine the placement of the OCT block because the RZQ pin can only be connected to its corresponding OCT block.
During calibration, the OCT matches the impedance seen on the external resistor through the rzqin port. Then, the OCT block generates two 16-bit calibration code words—one word calibrates the series termination and the other word calibrates the parallel termination. A dedicated bus sends the words serially to the OCT logic.
The enser signal, when triggered, specifies from which OCT block to read the calibration code words. The calibration code words are then buffered into the serial-to-parallel shift logic. After that, the Intel® FPGA OCT IP core asserts the S2PLOAD signal to send the calibration code words in parallel to the I/O buffers.
The calibration code words activate or deactivate the transistors in the I/O block, which will emulate series or parallel resistance to match the impedance.
In an Intel® Arria® 10 or Intel® Cyclone® 10 GX device, there is one OCT block in each I/O bank. Each OCT block requires an association with an external 240 Ω reference resistor through an RZQ pin.
The RZQ pin shares the same VCCIO supply with the I/O bank where the pin is located. An RZQ pin is a dual function I/O pin that you can use as a regular I/O if you do not use OCT calibration. When you use the RZQ pin for OCT calibration, the RZQ pin connects the OCT block to ground through an external 240 Ω resistor.
The following figures show how OCTs are connected in a single I/O column (in a daisy chain). An OCT can calibrate an I/O belonging to any bank, provided that the bank is in the same column and meets the voltage requirements. Because there are no connections between columns, OCT can only be shared if the pins belong to the same I/O column of the OCT.
The Intel® FPGA OCT IP core in power-up mode has two main interfaces:
- One input interface connecting the FPGA RZQ pad to the Intel® FPGA OCT block
- Two 16-bit words output which connect to I/O buffers
The Fitter does not infer a user-mode OCT. If you want your OCT block to use the user mode OCT feature, you must generate the Intel® FPGA OCT IP core. However, because of hardware limitations, you can only use one Intel® FPGA OCT IP core in user mode OCT in your design.
The FSM provides the following signals:
|IDLE||When you set the calibration_request vector, the FSM moves from IDLE state to CAL state. Keep the calibration_request vector at its value for two clock cycles. After two clock cycles, the FSM contains a copy of the vector. You must reset the vector to avoid reinitiating the calibration process.|
|CAL||During this state, the FSM checks which bits in the calibration_request vector were asserted and services them. The corresponding OCT blocks starts the calibration process that takes around 2,000 clock cycles to complete. After calibration completes, the calibration_busy signal is released.|
|Check Mask bit||The FSM checks each bit in the vector if the bit is set or not.|
|Shift Mask bit||This state simply loops over all the bits in the vector until it hits a 1.|
|Series Shift||This state serially sends the termination code from the OCT block to the termination logic. It takes 32 cycles to complete the transfer. After each transfer, the FSM check for any pending bits in the vector and services them accordingly.|
|Update Pending Bit||The pending register holds bits that corresponds to every OCT block in the Intel® FPGA OCT IP core. This state updates the pending register by resetting the serviced request.|
When the calibration_shift_busy signal is deasserted, you can assert s2pload to transfer the new termination codes into the buffers. You must assert the s2pload signal for at least 25 ns.
Because of hardware limitations, you cannot request another calibration until all bits in calibration_shift_busy vector are low.
The design example is a simple design that does not target any specific application. You can use the design example as a reference on how to instantiate the IP core.
To generate the design example files, turn on the Generate Example Design option in the Generation dialog box during IP core generation.
- The software generates the <instance>_example_design directory along with the IP core, where <instance> is the name of your IP core.
- The <instance>_example_design directory contains the make_qii_design.tcl scripts.
- After generating the IP core together with the design example files, run the following script at the command prompt: quartus_sh -t make_qii_design.tcl.
- If you wan to specify an exact device to use, use the following command: quartus_sh -t make_qii_design.tcl <device_name> .
|Number of OCT blocks||1 to 12||Specifies the number of OCT blocks to be generated. The default value is 1.|
|Use backwards-compatible port names||
||Check this to use legacy top-level names compatible with the ALTOCT IP core. This parameter is disabled by default.|
||Specifies whether OCT will be user-controlled or not. The default value is Power-up.|
|OCT block x calibration mode||
||Specifies the calibration mode for the OCT. X corresponds to the number of the OCT block. The default value is Single.|
|rzqin||Input||Input connection from RZQ pad to the OCT block. RZQ pad is connected to an external resistance. The OCT block uses impedance
connected to the rzqin port as a reference to generate the calibration code.
This signal is available for power-up and user modes.
|s2pload||Input||Asynchronous input signal to transfer the termination code from the termination logic block to the buffers. Assert this signal for at least 25 ns.|
|clock||Input||Input clock for user mode OCT. The clock must be 20 MHz or less.|
|reset||Input||Input reset signal. Reset is synchronous.|
|calibration_request||Input||Input vector for [NUMBER_OF_OCT:0]. Every bit corresponds to an OCT block. When a bit is set to 1, the corresponding OCT will calibrate, then serially shift the code word into the termination logic block. The request has to be held for two clock cycles. Due to hardware limitations, you must wait until the calibration_shift_busy vector to be zero until another request is issued; otherwise your request will not be processed.|
|calibration_shift_busy||Output||Output vector for [NUMBER_OF_OCT:0] indicating which OCT block is currently working on calibration and shifting termination codes to the termination logic block. When a bit is 1, it indicates that an OCT block is calibrating and shifting the code word to the termination logic block.|
|calibration_busy||Output||Output vector for [NUMBER_OF_OCT:0] indicating which OCT block is currently working on calibration. When a bit is 1, it indicates that an OCT block is calibrating|
|oct_<x>_series_termination control[15:0]||Output||16-bit output signal, with <x> ranging from 0 to 11. This signal connects to the seriesterminationcontrol port on the input/output buffer. This port sends the series termination code that calibrates Rs.|
|oct_<x>_parallel_termination_control[15:0]||Output||16-bit output signal, with <x> ranging from 0 to 11. This signal connects to the parallelterminationcontrol port on the input/output buffer. This port sends the parallel termination code that calibrates Rt.|
Intel® Arria® 10 and Intel® Cyclone® 10 GX devices have the following termination-related Intel® Quartus® Prime settings file (.qsf) assignments:
The input/output termination assignment specifies the termination value in ohm on the pin in question.
set_instance_assignment -name INPUT_TERMINATION <value> -to <pin name> set_instance_assignment -name OUTPUT_TERMINATION <value> -to <pin name>
To enable the series/parallel termination ports, include these assignments, which will specify the series and parallel termination values for the pins.
Make sure to connect the seriesterminationcontrol and parallelterminationcontrol ports from the Intel® FPGA OCT IP core to the Intel FPGA GPIO core.
set_instance_assignment -name INPUT_TERMINATION "PARALLEL <VALUE> OHM WITH CALIBRATION" -to <pin> set_instance_assignment -name OUTPUT_TERMINATION "SERIES <VALUE> OHM WITH CALIBRATION" -to <pin>
Directs the Fitter to make the proper connection from the desired OCT block to the specified pins. This assignment is useful when I/O buffers are not explicitly instantiated and you need to associate the pins with a specific OCT block.
set_instance_assignment -name TERMINATION_CONTROL_BLOCK <desired OCT BLK> -to <pin name>
This assignment is supported in Intel® Arria® 10 and Intel® Cyclone® 10 GX devices only. This assignment creates an Intel® FPGA OCT IP core without modifying the RTL.
The Fitter searches for the rzq pin name in the netlist. If the pin does not exist, the Fitter creates the pin name along with the Intel® FPGA OCT IP core and its corresponding connections. This allows you to create a group of pins to be calibrated by an existing or non-existing OCT and the Fitter ensures the legality of the design.
set_instance_assignment -name RZQ_GROUP <rzq pin name> -to <pin name>
Termination can exist on input and output buffers, and sometimes simultaneously.
There are two methods to associate pin groups with an OCT block:
- Use a .qsf assignment to indicate which pin (bus) is associated with which OCT block. You can use the TERMINATION_CONTROL_BLOCK or RZQ_GROUPassignment. The former assignment associates a pin with an OCT instantiated in the RTL while the latter associates the pin with a newly created OCT without modifying the RTL.
- Instantiate the I/O buffer primitives at the top level and connect them to the appropriate OCT blocks.
The IP migration flow allows you to migrate the ALTOCT IP core of Arria® V, Cyclone® V, and Stratix® V devices to the Intel® FPGA OCT IP core of Intel® Arria® 10 or Intel® Cyclone® 10 GX devices.
The IP migration flow configures the Intel® FPGA OCT IP core to match the settings of the ALTOCT IP core, allowing you to regenerate the IP core.
To migrate your ALTOCT IP core to the Intel® FPGA OCT IP core, follow these steps:
- Open your ALTOCT IP core in the IP Catalog.
- In Currently selected device family, select Arria 10 or Cyclone 10 GX.
Click Finish to open the
Intel® FPGA OCT IP core in the
The parameter editor configures the Intel® FPGA OCT IP core settings similar to the ALTOCT IP core settings.
- If there are any incompatible settings between the two, select new supported settings.
- Click Finish to regenerate the IP core.
- Replace your ALTOCT IP core instantiation in RTL with the Intel® FPGA OCT IP core.
|May 2017||2017.05.08||Rebranded as Intel.|