To avoid signal integrity issues, Altera recommends that you follow the design considerations, I/O placement guidelines, and board design guidelines for MAX® 10 devices regarding:
- I/O placement rules
- Voltage-referenced I/O standards
- High-speed LVDS, phase-locked loops (PLLs), and clocking
- External memory interfaces
- Analog to digital converter
Altera recommends that you perform SSN analysis early in your FPGA design, before the layout of your PCB.
The terminology used in this document includes the following terms:
- Aggressor: An output or bidirectional signal that contributes to the noise for a victim I/O pin
- PDN: Power distribution network
- QH: Quiet high signal level on a pin
- QHN: Quiet high noise on a pin, measured in volts
- QL: Quiet low signal level on a pin
- QLN: Quiet low noise on a pin, measured in volts
- SI: Signal integrity (a superset of SSN, covering all noise sources)
- SSN: Simultaneous switching noise
- SSO: Simultaneous switching output (which are either the output or bidirectional pins)
- Victim: An input, output, or bidirectional pin that is analyzed during SSN analysis. During SSN analysis, each pin is analyzed as a victim. If a pin is an output or bidirectional pin, the same pin acts as an aggressor signal for other pins.
In a sample system with three pins, two of the pins (A and C) are switching, while one pin (B) is quiet. If the pins are driven in isolation, the voltage waveforms at the output of the buffers appear without noise interference, as shown by the solid curves at the left of the figure. However, when pins A and C are switching simultaneously, the noise generated by the switching is injected onto other pins. This noise manifests itself as a voltage noise on pin B and timing noise on pins A and C.
Voltage noise is measured as the change in voltage of a signal due to SSN. When a signal is QH, it is measured as the change in voltage toward 0 V. When a signal is QL, it is measured as the change in voltage toward VCC.
Voltage noise can be caused by SSOs under two worst-case conditions:
- The victim pin is high and the aggressor pins (SSOs) are switching from low to high
- The victim pin is low and the aggressor pins (SSOs) are switching from high to low
SSN can occur in any system, but the induced noise does not always result in failures. Voltage functional errors are caused by SSN on quiet victim pins only when the voltage values on the quiet pins change by a large voltage that the logic listening to that signal reads a change in the logic value. For QH signals, a voltage functional error occurs when noise events cause the voltage to fall below VIH. Similarly, for QL signals, a voltage functional error occurs when noise events cause the voltage to rise above VIL. Because VIH and VIL of the Altera device are different for different I/O standards, and because signals have different quiet voltage values, the absolute amount of SSN, measured in volts, cannot be used to determine if a voltage failure occurs. Instead, to assess the level of impact by SSN, you can quantify the SSN in terms of the percentage of signal margin in Altera devices.
The figure shows four noise events, two on QH signals and two on QL signals. The two noise events on the right-side of the figure consume 50 percent of the signal margin and do not cause voltage functional errors. However, the two noise events on the left side of the figure consume 100 percent of the signal margin, which can cause a voltage functional error.
Noise caused by aggressor signals is synchronously related to the victim pin outside of the sampling window of a receiver. This noise affects the switching time of a victim pin but is not considered an input threshold violation failure.
PLLs are sensitive to SSN jitter generated by nearby I/O pins. Altera recommends that you do not use unterminated I/O standards in the same bank as the input clock signal to the PLL. Altera also recommends instantiating the input clock signal with full rail voltage.
Slower clock edges are more susceptible to jitter because the threshold range is wider than fast clock edges. Additionally, very slow clock edges are exposed to a larger amount of switching noise from the board to the device.
- Design with faster input clock edges.
- Set the unused pin to a programmable ground pin to help in shielding the signal interference.
- Terminate all unused pin. Unterminated unused pins can cause signal
interference between the input clock pin and the unused pins when there is signal
toggling. You can set the unused pin to:
- Weak pull-up resistor to create high impedance termination; or
- Programmable ground to help in shielding signal interference.
- Reduce the slew rate or current strength of the adjacent strong aggressor pin.
- Turn on the Schmitt trigger on the input buffer.
- Avoid using dedicated LVDS signal as single-ended input clock signal. The strong mutual coupling originally targeted for LVDS signals can create distortion on single–ended input clock signal coming from another LVDS terminal.
The Schmitt trigger input buffer has similar VIL and VIH as the LVTTL I/O standard but with better noise immunity. The Schmitt trigger input buffers are used as default input buffers during configuration mode.
The noise margin is measured at the VIH or VIL instead of the signal edges.
|Percentage of Simultaneous Switching Pins in I/O Bank||Recommended Maximum Data Input Signal Edge Rate|
|50% to 100%||0.6 V/ns|
|25% to 49%||1.0 V/ns|
|0% to 24%||1.5 V/ns|
If the data input signal exceeds the recommended signal edge rate, you can apply similar approach as the clock input signal to improve the signal integrity.
PLL Clock Input Pins
The PLL clock input pins are sensitive to SSN jitter. To avoid the PLL from losing lock, do not use the output pins directly on the left and right of the PLL clock input pins.
Data Input Pins
- The output pin directly adjacent to the data input pin is assigned an unterminated I/O standard, such as LVTTL and LVCMOS, with drive strength of 8 mA or higher.
- The output pin directly adjacent to the data input pin is assigned a terminated I/O standard, such as SSTL, with drive strength of 8 mA or higher.
To reduce jitter on data input pin, Altera recommends the following guidelines:
- Reduce the drive strength of the directly adjacent output pin for the different
unterminated I/O standards as follows:
- 4 mA or below—2.5 V, 3.0 V, and 3.3 V unterminated I/O standards
- 6 mA or below—1.2 V, 1.5 V, and 1.8 V unterminated I/O standards
- For unterminated I/O standard, assign the pins directly on the left and right of the data input pin to a non-toggling signal.
- For terminated I/O standard, you can use only one pin directly on the left or right of the data input pin as toggling signal, provided that you set the slew rate setting of this pin to “0” (slow slew rate). Otherwise, assign the pins directly on the left and right of the data input pin to a non-toggling signal.
- Change the unterminated I/O standard data input pin to a Schmitt Trigger input buffer for better noise immunity. If you are using Schmitt Trigger input buffer on the data input pin, you can use the directly adjacent output pin with unterminated I/O standard at a maximum drive strength of 8 mA.
|I/O Standard||Condition||Max Pins Per Bank (%)|
|2.5 V LVTTL/LVCMOS||16 mA current strength and 25 Ω OCT (fast and slow slew rate)||25|
|12 mA current strength (fast and slow slew rate)||30|
|8 mA current strength (fast and slow slew rate) and 50 Ω OCT (fast slew rate)||45|
|4 mA current strength (fast and slow slew rate)||65|
|2.5 V SSTL||—||100|
The Quartus® Prime software uses physics-based rules to define the number of I/Os allowed in a particular bank based on the I/O's drive strength. These rules are based on noise calculation to analyze accurately the impact of I/O placement on the ADC performance.
The physics-based rules are available for the following devices starting from these Quartus® Prime software versions:
- From Quartus® Prime version 14.1— MAX® 10 10M04, 10M08, 10M40, and 10M50 devices.
- From Quartus® Prime version 15.0.1— MAX® 10 10M02, 10M16, and 10M25 devices.
Altera highly recommends that you adhere to these guidelines to ensure ADC performance. Furthermore, following these guidelines prevents additional critical warning from future versions of the Quartus® Prime software when the physics-based rules are implemented.
|All||Disable all JTAG operation during ADC sampling. The ADC signal-to-noise and distortion ratio (SINAD) is not guaranteed during JTAG operation.|
|I/O Standards||TX||RX||Total||Availability (%)|
|I/O Standards||Bank 3||Bank 5||Bank 7||Device I/O Availability (%)|
|TX||RX||Availability (%)||TX||RX||Availability (%)||TX||RX||Availability (%)|
|I/O Standard Group||I/O Standards Name and Drive Strength|
- If you use a shared VREF pin as an I/O, all voltage-reference input buffers (SSTL, HSTL, and HSUL) are disabled.
- If you use a shared VREF pin as a voltage reference, you must enable the input buffer of specific I/O pin to use the voltage-reference I/O standards.
The voltage-referenced I/O standards are not
supported in the following I/O banks of these device packages:
- All I/O banks of V36 package of 10M02.
- All I/O banks of V81 package of 10M08.
- Banks 1A and 1B of E144 package of 10M50.
- For devices with banks 1A and 1B, if you use the VREF pin, you must supply a common VCCIO to banks 1A and 1B.
- Maximum number of voltage-referenced inputs for each VREF pin is 75% of total number of I/O pads. The Quartus® Prime software will provide a warning if you exceed the maximum number.
- Except for I/O pins that you used for static signals, all non-voltage-referenced output must be placed two pads away from a VREF pin. The Quartus® Prime software will output an error message if this rule is violated.
For LVDS applications, adhere to the I/O restriction pin connection guidelines to avoid excessive jitter on the LVDS transmitter output pins. The Quartus® Prime software generates a critical warning if these rules are violated.
- 3.3 V LVCMOS/LVTTL input buffers—enable clamp diode if VCCIO of the I/O bank is 3.0 V.
- 3.3 V or 3.0 V LVCMOS/LVTTL input buffers—enable clamp diode if VCCIO of the I/O bank is 2.5 V.
By enabling the clamp diode under these conditions, you will be able to limit overshoot or undershoot. However, this does not comply with hot socket current specification.
If you do not enable the clamp diode under these conditions, the signal integrity for the I/O pin will be impacted and there will be overshoot or undershoot problem. In this situation, you must ensure that your board design conforms to the overshoot/undershoot specifications.
|Voltage||Minimum (V)||Maximum (V)|
|VCCIO = 3.3 V||3.135||3.45|
|VCCIO = 3.0 V||2.85||3.15|
Two GPIOs Adjacent to DQ Pin Is Disabled
This limitation is applicable to MAX® 10 10M16, 10M25, 10M40, and 10M50 devices, and only if you use DDR3 and LPDDR2 SDRAM memory standards.
|Device Package||Memory Interface Width (DDR3 and LPPDR2 only)|
|F484||x8, x16, x24|
|F672||x8, x16, x24|
Total I/O Utilization in Bank Must Be 75 Percent or Less in Some Devices
If you use DDR3 or LPDDR2 SDRAM memory interface standards, you can generally use a maximum of 75 percent of the total number of I/O pins available in a bank. This restriction differs from device to device. In some devices packages you can use all 100 percent of the I/Os. The Quartus® Prime software will output an error message if the I/O usage per bank of that device is affected by this rule.
If you use DDR2 memory interface standards, you can assign 25 percent of the I/O pins as input pins only.
If a REFGND plane is not possible, route the analog input signal as adjacent as possible to REFGND.
There is one ADC reference voltage pin in each MAX® 10 device. This pin uses REFGND as ground reference. Keep the trace resistance less than 0.8 Ω.
- The ADC presents a switch capacitor load to the driving circuit. Therefore, the total RC constant, including package, trace, and parasitic driver must be less than 42.4 ns. This consideration is to ensure that the input signal is fully settled during the sampling phase.
- If you reduce the total sampling rate, you can calculate the required settling time as 0.45 ÷ FS > 10.62 × RC constant .
- To gain more total RC margin, Altera recommends that you make the driver source impedance as low as
Note: Not adhering to the source impedance recommendation may impact parameters such as total harmonic distortion (THD), signal-to-noise and distortion ratio (SINAD), differential non-linearity (DNL), and integral non-linearity (INL).
- For non-prescaler channel—less than 1 kΩ
- For prescaler channel—less than 11 Ω
- If possible, route the switching I/O traces on different layers.
- There is no specific requirement for input signal trace impedance. However, the DC resistance for the input trace must be as low as possible.
- Route the analog input signal traces as adjacent as possible to REFGND if there is no REFGND plane.
- Use REFGND as ground reference for the ADC input signal.
- For prescaler-enabled input signal, set the ground reference to REFGND. Performance degrades if the ground reference of prescaler-enabled input signal is set to common ground (GND).
Input Low Pass Filter Selection
- Altera recommends that you place a low pass filter to filter out high frequency noise being aliased back onto the input signal.
- Place the low pass filter as close as possible to the analog input signals.
- The cut off frequency depends on the analog input frequency. Altera recommends that the Fcutoff @ -3dB is at least two times the input frequency.
- You can download the ADC input SPICE model for ADC front end board design simulation from the Altera website.
|Driver||Board||Package||Pin Capacitance (pF)||RC Filter||Fcutoff @ -3dB (MHz)||Total RC Constant (ns)||Settling Time (ns)|
|R (Ω)||C (pF)||R (Ω)||C (pF)||R (Ω)||C (pF)||R (Ω)||C (pF)|
- To reduce IR drop and switching noise, keep the impedance as low as possible for the ADC power and ground. The maximum DC resistance for power is 1.5 Ω.
- The power supplies connected to the ADC should have ferrite beads in series followed by a 10 µF capacitor to the ground. This setup ensures that no external noise goes into the device power supply pins.
- Decouple each of the device power supply pin with a 0.1 µF capacitor. Place the capacitor as close as possible to the device pin.
There is no impedance requirement for the REFGND. Altera recommends that you use the lowest impedance with the most minimum DC resistance possible. Typical resistance is less than 1 Ω.
Altera recommends that you set a REFGND plane that extends as close as possible to the corresponding decoupling capacitor and FPGA:
- If possible, define a complete REFGND plane in the layout.
- Otherwise, route the REFGND using a trace that is as wide as possible from the island to the FPGA pins and decoupling capacitor.
- The REFGND ground is the analog ground plane for the ADC VREF and analog input.
- Connect REFGND ground to the system digital ground through ferrite beads. You can also evaluate the ferrite bead option by comparing the impedance with the frequency specifications.
- For DDR2, DDR3, and LPDDR2 interfaces, the maximum board skew between pins must be lower than 40 ps. This guideline applies to all pins (address, command, clock, and data).
- To minimize unwanted inductance from the board via, Altera recommends that you keep the PCB via depth for VCCIO banks below 49.5 mil.
- For devices with DDR3 interface implementation, onboard termination is required for the DQ, DQS, and address signals. Altera recommends that you use termination resistor value of 80 Ω to VTT.
- For the DQ, address, and command pins, keep the PCB trace routing length less than six inches for DDR3, or less than three inches for LPDDR2.
|March 2017||2017.03.02||Added a note to the guideline about the data input pin to specify that the signal to the input pin must be 1.5 V/ns or faster if an adjacent pin operates as a toggling output.|
|February 2017||2017.02.21||Rebranded as Intel.|
|December 2014||2014.12.15||Initial release.|