To manage signal integrity issues and protect the input pin, follow the guidelines in this document if you interface 3.3 V, 3.0 V, 2.5 V LVTTL or LVCMOS I/O systems with these Intel® device families:
- Cyclone® III
- Cyclone® IV
- Intel® Cyclone® 10 LP
- Intel® MAX® 10
To ensure device reliability and proper operation, you must design the I/O interfaces within the specifications recommended by the guidelines in this document.
The supported Intel® devices have one VCCIO voltage level per I/O bank. Additionally, the devices can also have driver input voltage levels for input signaling. Not all combinations of VCCIO and driver input voltage require attention with regards to the maximum input voltage.
Follow the guidelines in this document to manage the voltage overshoot and input requirements.
|Supported Intel® Device Receiver Bank VCCIO||LVTTL/LVCMOS Driver Voltage Level|
|2.5 V||3.0 V||3.3 V|
|2.5 V||No action required||
Disable diode and apply series termination or use driver selection table.
The devices' I/O pin is overdriven by a higher external voltage. You must meet the DC current specification of the diode.
Alternatively, you can apply series termination to manage voltage overshoot. In such cases, Intel recommends that you disable the diode due to the possible presence of a high DC current.
|3.0 V||No action required||No action required||No action required|
Apply series termination or use driver selection table.
Diode clamped voltage can still exceed the maximum DC and AC specifications due to the high VCCIO voltage level of the bank in which the I/O resides. You must manage the voltage overshoot. You can leave the diode enabled without concern for the DC current as the I/O pin is not overdriven.
- The conditions and actions in the preceding table apply only when the supported Intel® device's I/O pin is assigned as input, bidirectional, or tristated output using the 3.3/3.0/2.5 V LVTTL/LVCMOS I/O standards. No attention is required when the device's I/O pin is used as output only.
- The Intel® Quartus® Prime software enables the PCI-clamp diode on this pin for each of these conditions by default.
- Other I/O standards, such as 1.8 V, 1.5 V, or 1.2 V LVTTL or LVCMOS, 3.0 V PCI or PCI-X, voltage-referenced, and differential I/O standards, do not require attention on the maximum input voltage.
For more information about the absolute maximum DC input voltage and maximum allowed overshoot/undershoot voltage for the device families covered in this document, refer to the related information.
By default, if the assigned input, bidirectional, or tristated output pins use 3.3 V, 3.0 V, or 2.5 V LVTTL or LVCMOS I/O standards, the Intel® Quartus® Prime software enables the PCI clamp diode on the pin.
The PCI clamp diode can sufficiently clamp voltage overshoot to within the DC and AC input voltage specifications when the bank supply voltage (VCCIO) is 2.5 V or 3.0 V. You can clamp the voltage for a 3.3 V VCCIO to a level that exceeds the DC and AC input voltage specifications with ± 5% supply voltage tolerance. The clamped voltage is expressed as the sum of the supply voltage (VCCIO) and the diode forward voltage.
The PCI clamp diode in the supported Intel® devices can support a maximum of 10 mA DC current. The diode sinks the DC current when driven by a voltage level that exceeds the bank VCCIO plus the diode forward voltage. You must take the DC sink into consideration current when you interface a 2.5 V VCCIO receiver on the supported Intel® device with 3.0 V and 3.3 V LVTTL or LVCMOS I/O systems.
If you disable the diode in the Intel® Quartus® Prime software, ensure that the interface meets the DC and AC specifications.
If your system has the flexibility to accommodate a selection of driver strengths, you can also use the driver selection guideline to select the appropriate driver without using termination.
DC current exists when the diode is forward-biased. The amount of DC current depends on the driver output impedance, driver and receiver supply voltage, diode forward voltage, and a small resistance intrinsic to the transmission line.
- Set up the driver to drive static logic-high signal into the receiver of the supported Intel® device with the PCI clamp diode enabled.
- Apply the maximum supply voltage at the driver and the minimum VCCIO at the receiver of the supported Intel® device for the highest DC current.
Take the current measurement from the die pad of the supported
device—denoted by the red
pointer in the preceding figure.
You can obtain current measurements using a small sense resistor (in mili-Ω) placed in series to the transmission line.
You can significantly reduce voltage overshoot by matching the impedance of the driver to the characteristic impedance of the transmission line.
If the driver device manufacturer specifies the driver buffer output impedance, you can use the following equation to determine the apropriate series termination value:
R driver+R series≈Z 0
- R driver represents the intrinsic impedance of the driver
- R series represents the resistance of the external series resistor
If the output impedance value of the driver is not available, you can simulate an IBIS model for the driver to determind the appropriate series termination resistor value for the interface.
Some drivers offer series on-chip termination (OCT) to minimize impedance mismatch to the transmission line. You can select a driver with R driver that closely matches the transmission line impedance in such cases. OCT provides sufficient impedance matching without the expense of additional external component.
You must perform a simulation to determine the suitable series resistor value for your interface within the allowable tolerance condition. Choosing the appropriate resistor value for series termination is important:
- If the resistance is too small, the termination may not effectively reduce or eliminate the overshoot.
- If the resistance is too large, the driver may not sufficiently drive the transmission line and it can result in a stair-step response.
In this example, an Intel® FPGA with 3.3-V LVTTL 16 mA ouput is driven to a Cyclone® III 2.5-V LVTTL input. You can disable the diode and apply the series termination, or use the driver selection reference.
You must select a driver that meets the current limits of the supported Intel® device at the appropriate points in the I/V curve. You can obtain the I/V curve of the driver from the IBIS file provided by the device manufacturer.
You can also use slew rate control, if it is available on the driver, to address signal integrity concerns. Slew rate control allows you to reduce the edge rate of the output signal to help control voltage overshoot at the receiver. You must perform simulations to ensure that the specifications are met when using the slew rate feature.
Conformance to the voltage threshold specification ensures the correct logic-low and logic-high switching. On the other hand, conformance to the maximum DC and AC input specifications ensures the reliability of the receiver device in the system over an extended period.
A driver can drive to a supported Intel® device without requiring termination if the measured current of the driver is less than the current limit in the preceding table for the desired interface setup. The limits ensure that the DC and AC maximum input voltage specifications and maximum DC current for diode are met, if the driver current value is within the limits.
|Driver I/O Standard||VOH Level|
|2.5 V LVTTL||2.0 V|
|3.0 V LVTTL||2.4 V|
|3.0 V LVCMOS||VCCIO – 0.2 V|
|3.3 V LVTTL||2.4 V|
|3.3 V LVCMOS||VCCIO – 0.2 V|
The current limits in the following table takes into account the DC and AC requirements of the receiver, and the use of the PCI clamp diode. You can use the values as measurements to identify if a driver meets the input specifications of the supported Intel® device for the target I/O standard. Using these values, you can select the appropriate driver without performing simulation.
|Driver Voltage Level||Receiver Bank VCCIO(V)1|
|2.5 ± 5%||3.0 ± 5%||3.3 ± 5%|
|2.5 V LVTTL||No maximum limit||No maximum limit||48 mA|
|3.0 V LVTTL||26 mA||No maximum limit||26 mA|
|3.0 V LVCMOS||8 mA||No maximum limit||8 mA|
|3.3 V LVTTL||15 mA (30 mA) 2||No maximum limit||30 mA|
|3.3 V LVCMOS||4 mA (8 mA)2||No maximum limit||12 mA|
- The pull-up I/V curve represents the current and voltage behavior of the driver when it is sourcing logic-high.
- Take the measurement at the driver maximum allowable operating condition, which is at a low temperature and high supply voltage, to account for the worst possible overshoot condition.
- The current limit does not represent the current strength of a driver associated with a particular I/O standard.
- You must perform the measurement on the I/V curve at the maximum condition.
For the interface evaluation in these examples, the current strength of the Cyclone® device is 8 mA.
Input Setup with 2.5 V VCCIO
The supported Intel® device's on-chip PCI diode starts to sink the DC current IDC when driven by a steady state voltage greater than the sum of the supported Intel® device's VCCIO and diode forward voltage in the following figure. The diode is forward-biased when the driver's VCC is 3.3 V or 3.0 V and the IDC must not exceed 10 mA.
The amount of IDC through the diode is determined by the potential voltage difference between the driver and the supported Intel® device's pin, and the current capability of the driver. The diode can limit the transient voltage level to below the specification limit when the driver's VCC is 2.5 V—effectively limiting it to 3.325 V with the assumption that VCCIO is 2.625 V and diode forward voltage is 0.7 V.
Input Setup with 3.0 V VCCIO
The diode might not be forward-biased even when the driver's VCC is 3.3 V as the potential voltage difference between the driver's VCC and the supported Intel® device's VCCIO is less than the diode forward voltage. Therefore, there is no concern on IDC through the diode when driven with an input voltage level of 3.3 V, 3.0 V, or 2.5 V as shown in the following figure.
The forward-bias of the diode occurs only momentarily during overshoot conditions to clamp the overshoot voltage level. In such cases, the diode is effective in limiting the transient voltage level to below the specification limit—effectively limiting it to 3.85 V with the assumption that VCCIO is 3.15 V and diode forward voltage is 0.7 V.
Input Setup with 3.3 V VCCIO
IDC is almost zero at a steady input voltage level as the diode might not be forward-biased as shown in the setup in the following figure. At a higher VCC level of the driver, such as 3.465 V, the diode clamps transient voltage level at 4.165 V with the assumption that diode forward voltage is 0.7 V.
The use of a lower driver current capability reduces the voltage overshoot level. You must ensure that the duration of the overshoot is below these limits:
- For Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III devices, the percentage of high time for an overshoot of 4.15 V can be as high as 18.52% over a 10-year period.
- For Intel® MAX® 10 devices, the percentage of high time for an overshoot of 4.17 V can be as high as 11.7% over a 10-year period.
Obtain the IBIS model for the driver.
The model used as the driver is 1c_ttl33_io_d8 from the cyclone.ibs file. You can perform a DC sweep simulation on the HSPICE model and set the buffer to drive logic-high if the IBIS model is not available for the driver.
Open the IBIS file using the HyperLynx® Visual IBIS Editor.
The editor provides a graphical view of IBIS model data, which provides a measurement of the I/V values in graphical format.
Run the graphical view mode.
- Navigate to the 1c_ttl33_io_d8 model data from tree-view pane on the left column in the editor.
Right-click on the model denoted by [Model]
1c_ttl33_io_d8 and select View
A dialog box appears with multiple tabs for each data characteristic available for the model.
Select the pull-up I/V curve.
- Select the Pullup tab in the dialog window.
In the Display Curves list, select
Figure 12. Current Limit Measurement for IBIS Pull-Up Data Using Graphical Viewer HyperLynx Visual IBIS Editor. In the figure, the measured current is 33.8 mA.
Identify the appropriate VOH level and perform the current
Based on the driver selection reference, the VOH for the 3.3 V LVTTL driver is 2.4 V (see related information). Look for the maximum I/V curve and make the visual approximation current measurement at 2.4 V.
Identify allowed current limit.
Based on the maximum allowed current metrics for the supported Intel® device (see related information), the current limit is 30 mA for a 3.3 V LVTTL driver to a 3.3 V receiver bank of a supported Intel® device. The measured current exceeds the maximum allowed current limit.
|Driver I/O Standard||Drive Strength||Receiver Bank VCCIO(V)3|
|2.5 ± 5%||3.0 ± 5%||3.3 ± 5%|
|2.5 V LVTTL||4 mA||Yes||Yes||Yes|
|3.0 V LVTTL||4 mA||Yes||Yes||Yes|
|3.0 V LVCMOS||4 mA||Yes||Yes||Yes|
|3.3 V LVTTL||4 mA||Yes||Yes||Yes|
|3.3 V LVCMOS||2 mA||4||Yes||Yes|
|May 2016||2016.05.30||Corrected an error in the table listing the maximum allowed current metrics required to drive the supported devices without termination. The text in the last row has been corrected from "3.0 V LVCMOS" to "3.3 V LVCMOS".|
|March 2007||1.0||Initial release.|