The MAX® 10 devices consist of the following:
- Logic array blocks (LABs)
- Analog-to-digital converter (ADC)
- User flash memory (UFM)
- Embedded multiplier blocks
- Embedded memory blocks (M9K)
- Clocks and phase-locked loops (PLL)
- General purpose I/O
- High-speed LVDS I/O
- External memory interfaces
- Configuration flash memory (CFM)
- The amount and location of each block varies in each MAX® 10 device.
- Certain MAX® 10 devices may not contain a specific block.
Each LAB consists of the following:
- 16 logic elements (LEs)—smallest logic unit in MAX® 10 devices
- LE carry chains—carry chains propagated serially through each LE within an LAB
- LAB control signals—dedicated logic for driving control signals to LEs within an LAB
- Local interconnect—transfers signals between LEs in the same LAB
- Register chains—transfers the output of one LE register to the adjacent LE register in an LAB
The Intel® Quartus® Prime Compiler places associated logic in an LAB or adjacent LABs, allowing the use of local and register chain connections for performance and area efficiency.
The direct link connection minimizes the use of row and column interconnects to provide higher performance and flexibility. The direct link connection enables the neighboring elements from left and right to drive the local interconnect of an LAB. The elements are:
- M9K embedded memory blocks
- Embedded multipliers
Each LE can drive up to 48 LEs through local and direct link interconnects.
The control signals include:
- Two clock signals
- Two clock enable signals
- Two asynchronous clear signals
- One synchronous clear signal
- One synchronous load signal
|labclr1||Asynchronous clear signals:
|syncload||Synchronous load and synchronous clear signals:
You can use up to eight control signals at a time. Register packing and synchronous load cannot be used simultaneously.
Each LAB can have up to four non-global control signals. You can use additional LAB control signals as long as they are global signals.
An LAB-wide asynchronous load signal to control the logic for the preset signal of the register is not available. The register preset is achieved with a NOT gate push-back technique. MAX® 10 devices only support either a preset or asynchronous clear signal.
In addition to the clear port, MAX® 10 devices provide a chip-wide reset pin (DEV_CLRn) to reset all registers in the device. An option set before compilation in the Intel® Quartus® Prime software controls this pin. This chip-wide reset overrides all other control signals.
Each LE has the following features:
- A four-input look-up table (LUT) that can implement any function of four variables
- A programmable register
- A carry chain connection
- A register chain connection
- The ability to drive the following interconnects:
- Register chain
- Direct link
- Register packing support
- Register feedback support
Each LE input is directed to different destinations to implement the desired logic function. In both the normal or arithmetic operating modes of the LE, there are six available inputs:
- Four data inputs from the LAB local interconnect
- One LE carry-in from the previous LE carry-chain
- One register chain connection
Each LE has three general routing outputs:
- Two LE outputs drive the column or row and direct link routing connections
- One LE output drives the local interconnect resources
MAX® 10 devices support register packing. With register packing, the LUT or register output drives the three outputs independently. This feature improves device utilization by using the register and the LUT for unrelated functions.
The LAB-wide synchronous load control signal is not available if you use register packing.
Register Chain Output
Each LE has a register chain output that allows registers in the same LAB to cascade together. This feature speeds up connections between LABs and optimizes local interconnect resources:
- LUTs are used for combinational functions
- Registers are used for an unrelated shift register implementation
You can configure the programmable register of each LE for D, T, JK, or SR flipflop operation. Each register has the following inputs:
- Clock—driven by signals that use the global clock network, general-purpose I/O pins, or internal logic
- Clear—driven by signals that use the global clock network, general-purpose I/O pins, or internal logic
- Clock enable—driven by the general-purpose I/O pins or internal logic
For combinational functions, the LUT output bypasses the register and drives directly to the LE outputs.
The register feedback mode allows the register output to feed back into the LUT of the same LE. Register feedback ensures that the register is packed with its own fan-out LUT, providing another mechanism for improving fitting. The LE can also drive out registered and unregistered versions of the LUT output.
- Normal mode
- Arithmetic mode
These operating modes use LE resources differently. Both LE modes have six available inputs and LAB-wide signals.
The Intel® Quartus® Prime software automatically chooses the appropriate mode for common functions, such as counters, adders, subtractors, and arithmetic functions, in conjunction with parameterized functions such as the library of parameterized modules (LPM) functions.
You can also create special-purpose functions that specify which LE operating mode to use for optimal performance.
In normal mode, four data inputs from the LAB local interconnect are inputs to a four-input LUT. The Intel® Quartus® Prime Compiler automatically selects the carry-in (cin) or the data3 signal as one of the inputs to the LUT. LEs in normal mode support packed registers and register feedback.
The LE in arithmetic mode implements a two-bit full adder and basic carry chain. LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. Register feedback and register packing are supported when LEs are used in arithmetic mode.
The Intel® Quartus® Prime Compiler automatically creates carry chain logic during design processing. You can also manually create the carry chain logic during design entry. Parameterized functions, such as LPM functions, automatically take advantage of carry chains for the appropriate functions. The Intel® Quartus® Prime Compiler creates carry chains longer than 16 LEs by automatically linking LABs in the same column.
To enhanced fitting, a long carry chain runs vertically, which allows fast horizontal connections to M9K memory blocks or embedded multipliers through direct link interconnects. For example, if a design has a long carry chain in an LAB column next to a column of M9K memory blocks, any LE output can feed an adjacent M9K memory block through the direct link interconnect.
If the carry chains run horizontally, any LAB which is not next to the column of M9K memory blocks uses other row or column interconnects to drive a M9K memory block.
A carry chain continues as far as a full column.
The MAX® 10 embedded memory structure consists of 9,216-bit (including parity bits) blocks. You can use each M9K block in different widths and configuration to provide various memory functions such as RAM, ROM, shift registers, and FIFO.
MAX® 10 embedded memory supports the following general features:
- 8,192 memory bits per block (9,216 bits per block including parity).
- Independent read-enable (rden) and write-enable (wren) signals for each port.
- Packed mode in which the M9K memory block is split into two 4.5 K single-port RAMs.
- Variable port configurations.
- Single-port and simple dual-port modes support for all port widths.
- True dual-port (one read and one write, two reads, or two writes) operation.
- Byte enables for data input masking during writes.
- Two clock-enable control signals for each port (port A and port B).
- Initialization file to preload memory content in RAM and ROM modes.
- One 18-bit x 18-bit multiplier
- Up to two 9-bit x 9-bit independent multipliers
You can also use embedded multipliers of the MAX® 10 devices to implement multiplier adder and multiplier accumulator functions. The multiplier portion of the function is implemented using embedded multipliers. The adder or accumulator function is implemented in logic elements (LEs).
You can configure each embedded multiplier to support a single 18 x 18 multiplier for input widths of 10 to 18 bits.
The following figure shows the embedded multiplier configured to support an 18-bit multiplier.
All 18-bit multiplier inputs and results are independently sent through registers. The multiplier inputs can accept signed integers, unsigned integers, or a combination of both. Also, you can dynamically change the signa and signb signals and send these signals through dedicated input registers.
You can configure each embedded multiplier to support two 9 × 9 independent multipliers for input widths of up to 9 bits.
The following figure shows the embedded multiplier configured to support two 9-bit multipliers.
All 9-bit multiplier inputs and results are independently sent through registers. The multiplier inputs can accept signed integers, unsigned integers, or a combination of both.
- The Data A input of both multipliers share the same signa signal
- The Data B input of both multipliers share the same signb signal
Clock networks provide clock sources for the core. You can use clock networks in high fan out global signal network such as reset and clear.
PLLs provide robust clock management and synthesis for device clock management, external system clock management, and I/O interface clocking.
When the oscena input signal is asserted, the oscillator is enabled and the output can be routed to the logic array through the clkout output signal. When the oscena signal is set low, the clkout signal is constant high. You can analyze this delay using the TimeQuest timing analyzer.
The following figures show the physical locations of the PLLs. Every index represents one PLL in the device. The physical locations of the PLLs correspond to the coordinates in the Intel® Quartus® Prime Chip Planner.
The I/O elements are located in a group of four modules per I/O bank:
- High speed DDR3 I/O banks—supports various I/O standards and protocols including DDR3. These I/O banks are available only on the right side of the device.
- High speed I/O banks—supports various I/O standards and protocols except DDR3. These I/O banks are available on the top, left, and bottom sides of the device.
- Low speed I/O banks—lower speeds I/O banks that are located at the top left side of the device.
For more information about I/O pins support, refer to the pinout files for your device.
For more details about the modular I/O banks available in each device package, refer to the relevant device pin-out file.
The MAX® 10 devices use registers and logic in the core fabric to implement LVDS input and output interfaces.
- For LVDS transmitters and receivers, MAX® 10 devices use the the double data rate I/O (DDIO) registers that reside in the I/O elements (IOE). This architecture improves performance with regards to the receiver input skew margin (RSKM) or transmitter channel-to-channel skew (TCCS).
- For the LVDS serializer/deserializer (SERDES), MAX® 10 devices use logic elements (LE) registers.
The MAX® 10 devices do not contain dedicated serialization or deserialization circuitry:
- You can use I/O pins and core fabric to implement a high-speed differential interface in the device.
- The MAX® 10 solution uses shift registers, internal PLLs, and I/O elements to perform the serial-to-parallel and parallel-to-serial conversions of incoming and outgoing data.
- The Intel® Quartus® Prime software uses the parameter settings of the Altera Soft LVDS IP core to automatically construct the differential SERDES in the core fabric.
This capability allows you to use the MAX® 10 devices in a wide range of applications such as image processing, storage, communications, and general embedded systems.
The external memory interface solution in MAX® 10 devices consist of:
- The I/O elements that support external memory interfaces.
- The UniPHY IP core that allows you to configure the memory interfaces to support different external memory interface standards.
External memory interfaces support is available only for 10M16, 10M25, 10M40, and 10M50 devices.
The ADC solution consists of hard IP blocks in the MAX® 10 device periphery and soft logic through the Altera Modular ADC IP core.
The ADC solution provides you with built-in capability to translate analog quantities to digital data for information processing, computing, data transmission, and control systems. The basic function is to provide a 12 bit digital representation of the analog signal being observed.
The ADC solution works in two modes:
- Normal mode—monitors up to 18 single-ended external inputs with a cumulative sampling rate of one megasymbols per second (Msps).
- Temperature sensing mode—monitors internal temperature data input with a sampling rate of up to 50 kilosymbols per second (ksps).
Using the JTAG configuration scheme, you can directly configure the device CRAM through the JTAG interface—TDI, TDO, TMS, and TCK pins. The Intel® Quartus® Prime software automatically generates an SRAM Object File (.sof). You can program the .sof using a download cable with the Intel® Quartus® Prime software programmer.
You need to program the configuration data into the configuration flash memory (CFM) before internal configuration can take place. The configuration data to be written to CFM will be part of the programmer object file (.pof). Using JTAG In-System Programming (ISP), you can program the .pof into the internal flash.
During internal configuration, MAX® 10 devices load the CRAM with configuration data from the CFM.
The UFM is part of the internal flash available in MAX® 10 devices.
The UFM architecture of MAX 10 devices is a combination of soft and hard IPs. You can only access the UFM using the Altera On-Chip Flash IP core in the Intel® Quartus® Prime software.
- Data—a wrapper of the UFM block that provides read and write accesses to the flash.
- Control—the CSR and status register for the flash, that is required only for write operations.
MAX® 10 power optimization features are as follows:
- Single-supply or dual-supply device options
- Power-on reset (POR) circuitry
- Power management controller scheme
- Hot socketing
MAX® 10 single-supply devices only need either a 3.0- or 3.3-V external power supply. The external power supply serves as an input to the MAX® 10 device VCC_ONE and VCCA power pins. This external power supply is then regulated by an internal voltage regulator in the MAX® 10 single-supply device to 1.2 V. The 1.2-V voltage level is required by core logic operation.
MAX® 10 dual-supply devices require 1.2 V and 2.5 V for the device core logics and periphery operations.
The power management controller scheme allows you to allocate some applications in sleep mode during runtime. This enables you to to turn off portions of the design, thus reducing dynamic power consumption. You can re-enable your application with a fast wake-up time of less than 1 ms.
The MAX® 10 device offers hot socketing, which is also known as hot plug-in or hot swap, and power sequencing support without the use of any external devices. You can insert or remove the MAX® 10 device on a board in a system during system operation. This does not affect the running system bus or the board that is inserted into the system.
The hot-socketing feature removes some encountered difficulties when using the MAX® 10 device on a PCB that contains a mixture of devices with different voltage levels.
- Board or device insertion and removal without external components or board manipulation
- Support for any power-up sequence
- Non-intrusive I/O buffers to system buses during hot insertion
|February 2017||2017.02.21||Rebranded as Intel.|
|August 2016||2016.08.11||Removed content duplication in Embedded Multiplier.|
|September 2014||2014.09.22||Initial release.|