The I2C is a serial, two-wire, low-bandwidth, industry standard protocol used in embedded systems to communicate with various low-speed peripheral devices. The SPI is a widely used, fast, four-wire, full duplex, serial communication interface.
Many embedded systems today have SPI interfaces, making it difficult to connect them with peripheral devices in an I2C fashion. You can make the connection by modifying the system, but this is economically inefficient. The best solution is to use Altera devices as a bridge to connect the two interfaces.
You can use the MAX II, MAX V, or MAX 10 FPGA devices to implement the bridge. Altera devices provide greater flexibility, consume less power, and can be economically integrated into the embedded system. The MAX II, MAX V, or MAX 10 FPGA device acts as an SPI slave to the host (SPI master) and acts as a master to the I2C bus.
The provided designs enable an SPI-equipped host to control data flow to other devices such as Analog-to-Digital (AD) converter, LED controller, audio processor to read temperature sensors, hardware monitors, and diagnostic sensors that are on an I2C interface.
The bridge interfaces with the SPI host as an SPI slave using four wires, SS and SCLK signals for control, and MISO and MOSI signals for data. The side interfacing with the I2C bus has two wires, and SCLK and SDA signals.
Altera device acts as one of the slaves to the SPI master device.
|SS||Input (active low)||Slave select|
- command register (8 bits)
- data in (8 bits)
- status register (8 bits)
- data out (8 bits)
The SPI word length is fixed at 16 bits.
In every SPI word, the command register dictates the functions on the I2C bus, and the data in holds the data to be sent by the I2C bus. Similarly, the last bit of the status register is the acknowledge bit and the data out is the data received over the I2C line in the previous I2C cycle.
At the end of every SPI bus:
- The slave select line goes high; indicating a word complete.
- The master executes an I2C bus as per the value of command register at that time.
After a fixed delay, depending on the frequency of the I2C SCL, another SPI word can be sent. The minimum delay between two SPI words is the I2C SCL clock frequency.
Because the designs are meant to provide an interface between an SPI master and an I2C device, multi-master support is not provided on the I2C bus.
|SCLK||Output||I2C serial clock|
|SDA||Bidirectional||I2C data bus|
The I2C functions are carried out based on the command register value received from the SPI side.
|Command Register||Data In Register||Function on the I2C Line|
|10000000||Slave address + R/W||Start/repeat start|
|01000000||Data to be written||Write a byte|
|00100000||Don’t care||Read a byte|
|00000000||Don’t care||Null, wait state|
The data read in a particular I2C transaction is stored in the data out register and is read by the SPI master in its next SPI transaction. The last command word, 00000000 (b), is required for the SPI master to read the value of status and data out registers without doing anything on the I2C bus.
The MAX II design uses an EPM240 device. You can also implement this application in MAX V and MAX 10 devices.
|December 2007||1.0||Initial release.|