The SmartVID computing algorithm uses the device speed grade information and targets the operating voltage through fuse values to determine the desired voltage identification (VID) code. The SmartVID Controller IP core then sends the VID code to an external voltage regulator on a parallel interface. For Industrial speed grade, the SmartVID controller takes in additional input from on-die temperature sensor to perform a temperature compensated voltage change operation.
|IP Core Information||Core Features||
|Device Family||Supports Arria® 10 devices with –V power option.|
- Create a Quartus® Prime project using the New Project Wizard available from the File menu.
To enable the SmartVID operation, select an Arria 10 device with VID
capability (with OPN –V).
Contact Intel to obtain access to the Arria 10 device with–V power option.
- On the Tools menu, click IP Catalog.
Under Installed IP,
double-click Library > Low Power > SmartVID Controller IP.
The parameter editor appears.
- Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the targeted Intel device family and output file HDL preference. Click OK.
Specify parameters and options in the SmartVID Controller
- Specify parameters defining the IP core functionality and device-specific features.
- Specify options for processing the IP core files in other EDA tools.
- Click Generate to generate the IP core and supporting files, including simulation models.
- Click Close when file generation completes.
- Click Finish.
- If you generate the SmartVID Controller instance in a Quartus® Prime project, you are prompted to add Quartus® Prime IP File (.qip) and Quartus® Prime Simulation IP File (.sip) to the current Quartus® Prime project.
|Device family||Arria 10||This IP core is available only for Arria 10 devices with –V power option.|
|Core Speed Grade||–3, –2, or –1||Select the core fabric speed grade
of the FPGA.
Note: If you select –1, the SmartVID feature will not be enabled.
|Device Supports VID||Yes or No||Indicates if the device you selected supports the SmartVID feature.|
|Start operation||Yes or No||
|Enable SmartVID computation||Yes or No||Select No if you don't want to use the SmartVID feature.|
|Step size in VID code||5, 10, 15, 20, 25, 30, 35, 40, 45, 50||Select the difference value (mV) between two consecutive VID codes.|
|Minimum time for VID code update||10–1048||Select the duration that must elapse (ms) after the IP core reads the previous VID code and before it computes a new VID code.|
|JTAG||Uses the JTAG interface to retrieve the fuse value from the JTAG atom on an Arria 10 device.|
|Temperature Sensor||Uses the temperature sensor to sample the temperature code for the SmartVID controller operation.|
|Avalon Control and Status Register (CSR)||To change the control and status register values on the fly (for advance users).|
|Parallel/User Logic||To interface with the user logic.|
- After the deassertion of the reset signal, the SmartVID controller waits for bit 0 of the CC1 register (VID_OP_START) to be 1.
- When VID_OP_START is 1, the SmartVID controller reads the fuse value.
- Then vidctl_vid_code_avail goes high indicating a new VID code is available.
- The user logic interface asserts vidctl_vid_ack indicating that the new VID code is read.
- If you turned off the SmartVID feature in the parameter editor, the IP
core checks if the VID code is 0.9 V. If the VID code is less than 0.9 V, the IP core
starts incrementing the VID code by x value until the default value
0×30 is achieved. Then it waits for the SmartVID feature to be enabled.
Note: x value is the value defined in Step size in vid code in the parameter editor or through the VID_STEP SIZE register.
- If you turned on the SmartVID feature, the IP core checks if the device temperature grade is Extended (E) or Industrial. If the grade is E, the IP core decrements the VID code by x value which causes vidctl_vid_code_avail to go high.
- The user logic controller asserts vidctl_vid_ack so that new VID code can be computed. vidctl_vid_ack stays asserted until the VID code is updated. Every time, when a new VID code is computed, vidctl_vid_code_avail goes high. The VID code remains the same until the user logic controller asserts vidctl_vid_ack.
|vid_clk||Input||Must be 125 MHz. Most of the functional blocks in the IP core use this clock.|
|jtag_core_clk||Input||Must be 25 MHz. The fuse-read logic in the IP core uses this clock.|
|vid_rst_b||Input||An active-low reset synchronized to vid_clk domain.|
|vid_jtag_rst_b||Input||An active-low reset synchronized to jtag_core_clk domain.|
|vidctl_avmm_address[2:0]||Input||The Avalon-MM Master address for data transfer to/from SmartVID controller. This is a word address.|
|vidctl_avmm_read||Input||Read-transfer indication from the Avalon-MM Master to the SmartVID controller.|
|vidctl_avmm_readdata[31:0]||Output||Read data from SmartVID controller to Avalon-MM Master.|
|vidctl_avmm_write||Input||Write-transfer indication from the Avalon-MM Master to the SmartVID controller.|
|vidctl_avmm_writedata[31:0]||Input||Write data from the Avalon-MM Master to the SmartVID controller.|
|vidctl_vid_ack||Input||Acknowledge pulse of the vidctl_vid_code signal.|
|vidctl_temp[9:0]||Input||Connect this signal to the tempout port of the temperature sensor. This is the temperature code output from temperature sensor.|
|vidctl_eoc||Input||Connect this signal to the eoc port of the temperature sensor. This is the end of conversion signal from temperature sensor.|
|vidctl_tdocore||Input||Connect this signal to the tdocore port of the JTAG atom.|
|vidctl_ntrstcore||Output||Connect this signal to the ntrstcore port of the JTAG atom.|
|vidctl_tckcore||Output||Connect this signal to the tckcore port of the JTAG atom.|
|vidctl_corectl_jtag||Output||Connect this signal to the corectl port of the JTAG atom. Dynamic FPGA core firewall enable.|
|vidctl_tmscore||Output||Connect this signal to the tmscore port of the JTAG atom.|
|vidctl_tdicore||Output||Connect this signal to the tdicore port of the JTAG atom.|
|vidctl_temp_sense_enable||Output||Connect this signal to the corectl port of the temperature sensor. This is a core enable signal from the core to the temperature sensor.|
|vidctl_temp_sense_reset||Output||Connect this signal to the reset port of the temperature sensor. This is the reset signal from the core to the temperature sensor.|
|vidctl_vid_code_avail||Output||When asserted, vidctl_vid_code is valid.|
|vidctl_avs_status||Output||When asserted., it indicates that the SmartVID feature is enabled.|
|vidctl_vid_code[5:0]||Output||6-bit VID code from the SmartVID controller.|
|vidctl_temp_code[9:0]||Output||10-bit temperature code from the SmartVID controller.|
|vidctl_temp_code_valid||Output||When asserted, the vidctl_temp_code value is valid.|
The SmartVID Controller IP core uses the Avalon Memory-Mapped (Avalon-MM) interface for read and write operations in a memory-mapped system. The 32-bit non-bursting Avalon-MM slave interface allows upstream to access internal control and status registers.
The SmartVID Controller IP supports a basic one clock cycle transaction bus. Avalon-MM slave interface does not support byte enable access. Avalon-MM slave read and write data width is 32 bits (DWORD access).
|0x0||Capabilities and Control 1 (CC1)||Configures the capabilities of the SmartVID feature.|
|0x1||Capabilities and Control 2 (CC2)|
|0x2||Capabilities and Control 3 (CC3)|
|0x3||VID Fuse1 (VF1)||Stores VID fuse values [31:0]|
|0x4||VID Fuse2 (VF2)||Stores VID fuse values [63:32]|
|0x5||Temperature and Computed VID Codes (TCVC)||Stores a sampled temperature code, and a computed VID code.|
|31:2||Reserved||RO||This register is reserved for future use.|
|1||Temperature Sensor Enable||RW||A policy bit that governs whether the temperature sensor of the Arria 10 device is enabled in user mode.
Note: The temperature codes from the temperature sensor are also used by other Arria 10 sub-systems. Clear this bit only if enabling the temperature sensor may cause unexpected issues to the Arria 10 device.
|0||SmartVID Controller Start Operations (VID_OP_START)||RW||A policy bit that determines whether the IP core can start operating when it is out of reset.
Note: Set this to 1 only after programming all other configuration registers for this IP core.
|31:27||Reserved||RO||This register is reserved for future use.|
|26:21||VID Step Size (VID_STEP)||RW||
These bits determine the final adjustment magnitude of the computed VID code at the end of each computation, if applicable. Each step represents a 5 mV change.
|20:1||VID Computation Delay (VID_COMPUTE_DELAY)||RW||These bits represent the duration that must elapse (in µs)
before a new VID code is computed. The legal range for the delay is
10 ms to 1048 ms.
Ensure that this computation delay is longer than the time required for the following tasks:
Note: For optimum system considerations, you are recommended to program this computation delay to 10 ms, 100 ms, or 1 second interval, instead of at µs range. For example, 10 ms (10,000 µs) = 00000010011100010000 (2710h).
|0||Dynamic SmartVID Feature Control (DYN_AVS_CONTROL)||RW||This bit dynamically enables or disables the SmartVID feature.
Note: The SmartVID logic in the IP core is only enabled when CC2, CC3, CC3, and VF1 bits are 1.
|31:17||Reserved||RO||This register is reserved for future use.|
|16||Device Supports SmartVID Feature (DEVICE_SUPPORTS_AVS)||RO||This policy bit determines if the SmartVID feature can be
|15:10||Live VID Code (VID_DEFAULT)||RO||This bit indicates the live VID code produced by the SmartVID Controller IP core. This live code may be in either static mode or SmartVID mode.|
|9:4||Default VID Value (VID_DEFAULT)||RO||These bits indicate the default VID value.|
|3||SmartVID Feature Enable (AVS_ENABLE)||RO||This policy bit determines if the SmartVID feature can be enabled.|
|2:1||Core Speed Grade (CORE_SPEED_GRADE)||RO||
These bits indicate the core fabric speed grade of the FPGA device.
|0||Reserved||RO||This register is reserved for future use.|
|31||Reserved||RO||This register is reserved for future use.|
|30||VID Fuses Valid||RO||This bit indicates whether the non-reserved fields of this register have valid values or not.
|29:24||VID for –1 Core Speed Grade||RO||These bits are mapped to the retrieved VID Fuse[29:24], which represent the
VID code for –1 core speed grade.
Refer to VID Codes for Arria 10 Speed Grades.
|23:22||Reserved||RO||This register is reserved for future use.|
|21:16||VID for –2 Core Speed Grade||RO||These bits are mapped to the retrieved VID Fuse[21:16], which represent the
VID code for –2 core speed grade.
Refer to VID Codes for Arria 10 Speed Grades.
|15:14||Reserved||RO||This register is reserved for future use.|
|13:8||VID for –3 Core Speed Grade||RO||These bits are mapped to the retrieved VID Fuse[13:8], which represent the
VID code for –3 core speed grade.
Refer to VID Codes for Arria 10 Speed Grades.
|7:5||Reserved||RO||This register is reserved for future use.|
|4||SmartVID Feature Enable Via Fuse||RO||This bit is mapped to the retrieved VID Fuse, which determines if the SmartVID feature
of the IP core can be supported.
|3:0||Reserved||RO||This register is reserved for future use.|
|31:28||Reserved||RO||This register is reserved for future use.|
|27||SmartVID Status||RO||This bit indicates the operating state of the SmartVID
feature in the .
|26:17||Temperature Used In SmartVID Computation||RO||These bits capture the temperature code used in the latest
computed VID code when SmartVID logic is active. This information is
intended for correlation and debugging purposes.
Note: These bits are set to 0 if CC1 and CC1 bits are 0 and the SmartVID logic is deactivated.
|16||Temperature Code Valid||RO|| This bit indicates whether TCVC[9:0] has a valid temperature
Note: This bit is set to 0 if CC1 is 0.
|15:10||Latest Computed VID Code in SmartVID mode||RO||These bits indicate the latest computed VID code when SmartVID logic is active. When SmartVID logic is deactivated, these bits will be set to 0.|
|9:0||Temperature Code||RO|| These bits indicate the periodically sampled temperature
code output by the temperature sensor.
Note: These bits are set to 0 if CC1 is 0.
Voltage = (VID Code–28)×0.005V+0.8V
|VID Code (Binary)||Voltage (V)|
When the CC1 register is 1, the IP core initiates VID fuse-read. The SmartVID Controller IP core then switches to SmartVID mode when the following conditions are met:
- SmartVID logic enabled.
- The external controller reads out the default VID value and asserts vidctl_vid_ack.
- The duration specified in the CC2[20:1] register elapses.
- Reset synchronizer
- Voltage regulator
- Designed to remap the VID code from the SmartVID controller IP core to the corresponding voltage code of the targeted voltage regulator.
- Temperature sensor
- JTAG block
- The reference design uses an IOPLL to generate the required 125 MHz and 25 MHz clocks. These clocks can also be supplied by a customer design if the reference design is used as a template to add the SmartVID feature.
|May 2017||2017.05.08||Rebranded as Intel.|
|May 2015||2015.05.04||Updated the legal range for the VID Computation Delay (VID_COMPUTE_DELAY) register from 1 ms–1 second to 10 ms–1 second.|
|December 2014||2014.12.15||Initial release.|