These guidelines facilitate board designs for the DisplayPort and HDMI IP video interfaces.
- Main Link—Main Link transports video and/or audio streams and supports up to 4 lanes at 5.46 Gigabits per second (Gbps) per lane.
- AUX Channel—The DisplayPort source and sink devices use AUX Channel for link and device management.
- Hot Plug Detect (HPD)—The DisplayPort sink device uses HPD to announce its presence or when it requires the attention of the DisplayPort source device.
The Main Link consists of one, two, or four doubly terminated differential pairs or lanes with AC coupling. The figure below depicts a Main Link lane with an FPGA transceiver PHY, a redriver, and AC-coupling caps.
The FPGA transceiver PHY includes on-chip termination. The on-chip Vbias_TX (or Vbias_RX) voltage is an internally generated common mode voltage. The redriver devices compensate for frequency-related signal loss and cleans up jitter. An example of a DisplayPort 1.2 redriver device is TI SN75DP130 used in the Bitec DisplayPort daughter card.
Altera recommends that you use DisplayPort redriver devices such as TI SN75DP130 to achieve reliable signal integrity under various DisplayPort channel condition.
|Devices||DisplayPort Source Redriver||DisplayPort Sink Redriver|
|Arria V GX/GT/GZ||Recommended||Required|
|Cyclone V GT||Recommended||Required|
|Stratix V GX/GT/GZ||Recommended||Required|
For more information about the DisplayPort 1.2 redriver device, TI SN75DP130, refer to the SN75DP130 DisplayPort 1:1 Redriver With Link Training datasheet.
- Use 135-MHz clock with minimal jitter for the DisplayPort transceiver PHY reference clock. Feed the 135-MHz clock directly through the REFCLK pin of the transceiver bank.
- Use no more than two vias per trace and avoid via stubs.
- Match the differential pair impedance to the impedance of the connector and cable assembly (100 ohm ±10%).
- Minimize inter-pair and intra-pair skews to meet the Main Link skew requirement.
- Avoid routing a differential pair over a gap in the underneath plane.
- Use standard high speed PCB design practices.
The 100-KΩ and 1-MΩ pull-up and pull-down resistors are placed between the connectors and AC-coupling capacitors. These resistors help detect any DisplayPort upstream devices, including a powered DisplayPort upstream device by a Sink device.
|AUX Direct Current (DC) Common Mode Voltage||0.0 V||2.0 V||Common mode voltage is equal to Vbias_TX (or Vbias_RX)|
|AUX Peak-to-Peak Voltage||0.29 V||1.38 V||Differential peak-to-peak voltage swing|
|AUX AC-Coupling Capacitor||75 nF||200 nF||The AUX channel AC-coupling capacitors are placed on both the DisplayPort upstream and downstream devices.|
The BLVDS I/O is a bidirectional differential I/O interface and requires special pin assignment consideration. Depending on the FPGA bank VCCIO voltage and I/O standard used, the BLVDS I/O may require a series resistor, Rs. The series resistor ensures the AUX channel differential voltage swing is below the maximum peak-to-peak voltage swing specification.
|FPGA Device||Pin||I/O Standard||VCCIO||Series Resistor (Rs) Value|
|Arria 10||LVDS||Differential HSTL -12||1.2 V||0 Ω|
|Differential SSTL-18 Class II||1.8 V||22 Ω|
|Arria V, Cyclone V, and Stratix V||DIFFIO_RX 1||Differential SSTL-2 Class II||2.5 V||100 Ω|
The TI SN65MLVD200A device is powered by 3.3V, and its single-ended FPGA interface signals use LVTTL voltage level. If your FPGA device's I/O voltage (VCCIO) is not compatible with LVTTL, use a voltage level translator such as TI TXS0108. The SN65MLVD200A differential peak-to-peak voltage swing meets the DisplayPort AUX channel electrical specification.
For more information about the BLVDS driver, TI SN65MLVD200A, refer to the SN65MLVD20xx Multipoint-LVDS Line Driver and Receiver datasheet.
To assist the upstream Source detection by the Sink, the upstream Source pulls down AUX+ and pulls up AUX- signal using 100-KΩ resistors. The downstream Sink weakly pulls up AUX+ and pulls down AUX- signal using 1-MΩ resistors.
|RX_SENSE_P||Upstream source device is detected or DisplayPort cable is plugged in.||Upstream source device is not detected or DisplayPort cable is unplugged.|
|RX_SENSE_N||Upstream source device is not powered up.||Upstream source device is powered.|
The DisplayPort Source and Sink devices pull down the HPD with a ≥ 100 kΩ resistor.
The TMDS channels carry video, audio, and auxiliary data. The DDC is based on I2C protocol. The HDMI uses the DDC to read Extended Display Identification Data (EDID) and exchange configuration and status information between an HDMI Source and Sink.
HDMI 2.0 TMDS data channels support up to 6 Gbps. Altera HDMI Source requires 4 transceiver channels for three data channels and one clock channel. Altera HDMI Sink uses 3 transceiver channels for TMDS data channels.
Altera recommends using an HDMI 2.0 redriver device to ensure reliable signal integrity under various TMDS channel conditions.
The following figure shows the FPGA transceiver PHY connection with a redriver/level shifter device using AC coupling. An example of an HDMI 2.0 redriver/level shifter device is Pericom PI3HDX1204, used in the Bitec HDMI 2.0 daughter card. The on-chip termination is enabled by default.
The following figure shows the FPGA transceiver PHY connection with a redriver/equalizer device using AC coupling. An example of an HDMI 2.0 redriver/equalizer device is Pericom PI3HDX1204, used in the Bitec HDMI 2.0 daughter card. The on-chip termination is enabled by default.
Altera HDMI design examples provided in the Quartus II altera_hdmi install directory require a Bitec HDMI daughter card. Depending on the FPGA development board connector type, you would need either a HSMC or FMC HDMI daughter card.
For more information about the Pericom PI3HDX1204 HDMI 2.0 redriver, refer to the datasheet.
- Use no more than two vias per trace and avoid via stubs
- Match the differential pair impedance to the impedance of the connector and cable assembly (100 ohm ±10%)
- Minimize inter-pair and intra-pair skew to meet the TMDS signal skew requirement
- Avoid routing a differential pair over a gap in the underneath plane
- Use standard high speed PCB design practices
To interface with an FPGA, you need to translate the 5V SCL and SDA signal level to the FPGA I/O voltage level (VCCIO) using a voltage level translator such as TI TXS0102 used in the Bitec HDMI 2.0 daughter card. The TI TXS0102 voltage level translator device integrates internal pull-up resistors so that no on-board pull-up resistors are needed.
To interface with an FPGA, you need to translate the 5V HPD signal to the FPGA I/O voltage level (VCCIO), using a voltage level translator such as TI TXB0102, which does not have pull-up resistors integrated. An HDMI Source needs to pull down the HPD signal so that it can reliably differentiate a floating HPD signal and a high voltage level HPD signal.
An HDMI Sink +5V Power signal must be translated to FPGA I/O voltage level (VCCIO). The signal must be weakly pulled down with a resistor (10K) to differentiate a floating +5V Power signal when not driven by an HDMI Source. An HDMI Source +5V Power signal has over-current protection of no more than 0.5A.
|November 2015||2015.11.02||Initial release.|