The Altera PHYLite for Parallel Interfaces IP core (or Altera PHYLite IP core) enables your design to achieve better timing performance. Intel recommends that you use the Altera PHYLite IP core for general purpose I/O (GPIO) data rates higher than 200 Mbps to achieve optimal out signal.
Switching an Altera GPIO design to the Altera PHYLite IP core is very resource intensive.
- The Altera PHYLite IP core uses up the IOPLL, the phy_clk network, in the particular I/O bank.
- You may not be able to use the external memory interfaces and the Altera PHYLite IP core as normal memory protocols in this I/O bank unless they operate at the frequency multiplication of the Altera GPIO interface being switched.
- You also cannot use the Altera LVDS SERDES IP core in the same I/O bank with Altera PHYLite IP core.
- Generate a PHYLite design in the Quartus® Prime software. Customize the design based on the Parameter Settings.
Connect the modules and the input and output ports, as shown in the
Figure 1. Input InterfaceFigure 2. Output Interface
|Number of groups||1||–|
|Interface clock frequency||Configure the frequency based on the required data rate.||The interface clock frequency is equal to data rate speed for SDR and half of the data rate speed for DDR.|
|Use core PLL reference clock connection||Turn on if your reference clock source is from the output of PLL or clock source from the core.||–|
|Use recommended PLL reference clock frequency||
Turn on if the default frequency matches your reference clock frequency.
Else, turn off the option and choose the desired reference clock frequency from the drop down list.
|Clock rate of user logic||Specify the clock frequency to full, half, or quarter, based on the core logic.||For example, if the data rate speed sent from the FPGA to the external device is toggling at 200 Mbps in DDR mode, a half rate interface means that the user logic in the FPGA runs at 100 MHz.|
|I/O standard||Specify the desired I/O standard.||–|
Note: In the Altera PHYLite IP core, the strobe_in and strobe_out ports are equivalent to the source synchronous clock interface to the input and output data.
|Pin type||Specify based on the direction of the data pins.||–|
|Pin width||Specify the desired data width.||–|
|DDR/SDR||Specify the desired data rate mode.||–|
(When you configure the Altera PHYLite IP core as an input interface.)
Specify the expected read latency.
|For example, a design with an external clock frequency of 100 MHz in full rate has a valid read latency of 3–63 external interface clock cycles.|
|Capture strobe phase shifty||Configure based on the desired phase shift of the input strobe relative to the input data.||For example in DDR mode, configure the phase shift to 90° would shift the edge-aligned input data/strobe to center-alignment at the read FIFO.|
(When you configure the Altera PHYLite IP core as an output interface.)
|Specify a value within 0–3||Indicates the number of external interface clock cycles to delay the output data.|
|Use output strobe||Turn on if you want to enable the output strobe pin.||–|
|Output strobe phase||Specify based on the desired phase relationship between data and strobe being output from the IP core.||For example in DDR mode, configuring the phase shift to 90° would shift the strobe to center align with the output data|
|Data configuration||Specify the pin configuration of the data to be used as single ended or differential signaling.||–|
|Strobe configuration||Specify the type of strobe pin configuration to be used as single ended or differential signaling.||–|
|Use Default OCT Values||Turned on by default.||Turn off if you want to configure your desired input or output OCT values or you do not want any termination.|
|Generate Input/Output Delay Constraints for this group||Turned on by default.||Specifies the input/output delay setup or hold constraint against the input/output strobe of the group.|
|Altera GPIO IP Core||Direction||Altera PHYLite IP Core|
|interface_locked||Input/Output||Similar to the lock signal from the I/O phase locked loop (IOPLL). Typically the Altera GPIO IP core uses the IOPLL to generate the clock signal.|
|core_clk_out||Input/Output||Similar to the clock signal used for periphery-to-core or core-to-periphery transfer in the Altera GPIO IP core.|
|rdata_en||Input||Drive this signal high to ensure the input data/strobe port is always ready to receive incoming data.|
|strobe_in||Input||Sampling clock for the Altera PHYLite IP core that captures the input data.|
|strobe_out||Output||A generated clock/strobe signal from the PHYLite IP core. Similar to the synchronous clock out signal when using the GPIO IP core.|
|strobe_out_en||Output||Drive this signal high to ensure the Altera PHYLite IP core is always generating the source synchronous clock/strobe through the strobe_out port.|
|strobe_out_in[1:0]||Output||Tie strobe_out_in to high and strobe_out_in to low to generate a clock signal. This interface signal is generated in a similar manner you use the Altera GPIO IP core to generate the clock signal.|
|rdata_valid||Input||An output signal from the Altera PHYLite IP core that indicates the IP core has transmitted the data and the data is ready to be captured by the user logic.|
|Input/Output||SDR/DDR||Architecture||Clock Network||Worst Setup Slack||Worst Hold Slack||Slack Window (Setup + Hold)1|
|Input/Output||SDR/DDR||Architecture||Clock Network||Worst Setup Slack||Worst Hold Slack||Slack Window (Setup + Hold)|
|Input (1-bit Input)||DDR||
|Output (1-bit Input)||DDR||
In summary, the timing analysis on the source synchronous I/O implementation on the PHYLite IP core provides much larger timing slack window compared to the GPIO IP core. The PHYLite IP core uses the PHY clock network instead of the global clock networks in the core. The change in the clock network enables the PHYLite IP core to achieve better timing performance and avoid core noise effect.
The oscillator clock goes into the FPGA GCLK network to drive the output data through GPIO to Off-chip. Off-chip clock uses the shared oscillator. The clock source of the other user logic comes from the PLL clock out.
You can use one of the two following methods to migrate the GPIO to Altera PHYLite IP core using the output clock from the IOPLL supplied to the user logic:
- Generate the output clock from the Altera PHYLite IP core's output clock.
Figure 5. Generating Output Clock from PHYLite Output Clock
- The PHYLite IP core can export 4 additional IOPLL output clocks based on the specified configuration.
- You can calculate the actual support clock frequency based on the
Output Clock Frequency = VCO Frequency/ c Counter
- c Counter = Integers within 1–511
- Voltage-controlled oscillator (VCO) frequency = (Memory/Interface
clock frequency) × (VCO frequency multiplication factor)
Note: Refer to the Altera PHYLite for Parallel Interfaces IP core parameter editor for more information.
- Instantiate a new IOPLL in the adjacent I/O bank (where the PHYLite block
resides), if the Altera PHYLite IOPLL output clocks do not
support the desired output clock frequency.
Figure 6. Instantiating a New I/O PLL
To migrate the multi-speed parallel interface GPIO solution to Altera PHYLite, you must split the solution into two different I/O banks to run at different data rate.
You can manually set the pin to use 3.0V/2.5V I/O standard through the Quartus Prime assignment editor.
Generate the output clock through the PHYLite IP core if you use a regular I/O.
Generating the recovered clock through a dedicated clock out pin from the IOPLL or through the Altera PHYLite IP core results in equivalent jitter performance. The preferred solution is to use the IOPLL, because using the Altera PHYLite IP core is resource intensive.
The Altera GPIO to Altera PHYLite design example provides the Altera PHYLite configuration to mimic the GPIO input and output path usage and the expected behavior in simulation and hardware.
- Pattern generator (tx_data_output) to generate fixed serial 1100 pattern transmitting through the Altera PHYLite output (ddr_out)
- Two Altera PHYLite instances configured to mimic the GPIO input and output path usage to transmit and receive source synchronous data respectively.
The reset_n signal connects to the push button switch to control the reset port for the pattern generator and Altera PHYLite input and output instances.
- Arria® 10 FPGA development kit
- Loopback FPGA Mezzanine Card (FMC) attached to the FMC port B (FMCB)
- Intel® FPGA Download Cable II
The design example demonstrates a simple loopback that loops back the fixed serial 1100 pattern transmitted from the Altera PHYLite output (ddr_out) to the Altera PHYLite input (ddr_in) through the Loopback FMC daughter card.
The Altera PHYLite output signals from the dataout and clkout pins connect directly to the data_in and strobe_in pins that feed the Altera PHYLite input.
The data received from the Altera PHYLite input after you program the SOF in the Signal Tap Logic Analyzer should be the same as the data transmitted from the IP core through the Altera PHYLite output.
|May 2017||2017.05.08||Rebranded as Intel.|
|December 2016||2016.12.30||Edited the link to the design files.|
|December 2015||2015.12.14||Initial release.|