|VHDL compilation and simulation are not supported in the current release.||You can only simulate in Verilog in the current release.|
The automatically generated simple DMA design example has timing issues.
This timing problem does not affect DMA designs that use the internal descriptor controller or DMA designs that use an external DMA controller to drive the internal Read and Write Data Movers. These designs close timing and function correctly in hardware.
|You can simulate the simple DMA design and successfully and generate an SRAM Object file (*.sof). However, if you download the *.sof to hardware, the hardware will fail.|
Single Root I/O Virtualization (SR-IOV) support for H-Tile variants is preliminary in the 17.1 release.
|You can enable SR-IOV using the parameter editor. SR-IOV supporst basic simulation and compilation. However, SR-IOV is not fully verified. You may find functional problems in the current release.|
|The Root Port is preliminary in the 17.1 release.||You can enable the Root Port using the parameter editor. The Root Port supports basic simulation and compilation. However, the Root Port is not fully verified. You may find functional problems in the current release.|
|The Avalon® Memory-Mapped ( Avalon® -MM) DMA functionality is preliminary in the 17.1 release.||You can use the Avalon® -MM DMA functionality in the current release. Avalon® -MM supports simulation and compilation. However, this functionality has not been fully verified. You may find functional problems.|
|Upon reboot, the Intel® Stratix® 10 Hard IP for PCI Express® IP Core might be unable to exit BIOS enumeration.||This problem affects L-Tile ES1 and ES2 and H-Tile ES1 devices. It will be fixed in a a future release.|
The link acknowledge logic in the Intel® Stratix® 10 H-Tile ES2 devices has a encoding error. This encoding error results in the following incorrect link widths:
|This problem will be fixed in a future release.|