|IP Core Information||Core Features||
Monitors the following:
Supports access from the following:
|Device Family||Supports Arria® 10 devices|
|Device Tools||Quartus® Prime software|
The Quartus® Prime software includes installation of the Altera Voltage Sensor IP core.
- Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no project open, select the Device Family in IP Catalog.
- Type in the Search field to locate any full or partial IP core name in IP Catalog.
- Right-click an IP core name in IP Catalog to display details about supported devices, to open the IP core's installation folder, and for links to IP documentation.
- Click Search for Partner IP to access partner IP information on the web.
The parameter editor prompts you to specify an IP variation name, optional ports, and output file generation options. The parameter editor generates a top-level Quartus® Prime IP file (.ip) for an IP variation in Quartus® Prime Pro Edition projects.
The parameter editor generates a top-level Quartus IP file (.qip) for an IP variation in Quartus® Prime Standard Edition projects. These files represent the IP variation in the project, and store parameterization information.
Follow these steps to instantiate the Altera Voltage Sensor IP core parameters and options.
- Create a Quartus® Prime project using the New Project Wizard available from the File menu.
- On the Tools menu, click IP Catalog.
- Under Installed IP, double-click Library> Basic Functions> Configuration and Programming> Altera Voltage Sensor.
- Specify an entity name for the custom IP variation and select the targeted Altera device family. Click OK.
- In the Altera Voltage Sensor parameter editor, specify the core variant and the memory type for your application.
- Click Generate HDL and proceed to the next prompt window.
- Click Generate to generate the IP core and supporting files, including simulation models.
- Click Close when file generation completes.
- Click Finish.
You can use the GUI parameters to configure the Altera Voltage Sensor IP core.
|Core Variant||There are two configuration variants of the Altera Voltage Sensor IP core. Select the core variant that meets your requirement. For more information, refer to the related information.|
|Memory Type||Select the memory type that you use to store the voltage sample—on-chip memory or register.|
The Altera Voltage Sensor IP core consists of the following:
- voltage sensor controller core
- sample storage core
The voltage sensor controller core contains command register and conversion sequence data. You can use the command register to configure your intended conversion mode. This core also contains control logic which communicates with the voltage sensor hard IP block. You can access the register through the Avalon Memory-Mapped (Avalon-MM) slave interface. This core uses the Avalon Streaming (Avalon-ST) interface to send response.
This voltage sensor controller core receives commands through the Avalon-MM slave control and status register (CSR) interface. The command includes mode and sequences. This core decodes the command and drives the signals that are connected to the voltage sensor controller core accordingly.
The voltage sensor controller core supports 3 defined sequences:
- Channel 0 to Channel 1
- Channel 0 to Channel 7
- Channel 2 to Channel 7
This core allows you to monitor separate channels. You can configure the sequences during run time.
The voltage sensor controller core supports two modes of conversion that you can control using the command register.
When you set the RUN bit, conversion starts with either sequence or channel (by setting MD bits) and stops when a conversion is complete. The hardware automatically clears the RUN bit.
When you set the RUN bit, conversion starts with either sequence or channel (by setting MD bits) and when a conversion is complete, the conversion repeats the same set of conversion again. For example, if you choose the sequence for Channel 0 to Channel 7, the IP block restarts the whole sequence when the Channel 7 sample is complete. For a single channel read (MD = 2'b11), the IP block reads the value from that channel until the RUN bit is cleared. In this continuous conversion mode, the software clears the RUN bit.
The sample storage core stores voltage samples. The control core passes the voltage samples to this core through the Avalon-ST interface. The on-chip RAM stores the voltage samples and you can retrieve them through the Avalon-MM slave. This core provides an option to generate an interrupt when it retrieves a block of voltage samples using one full round of conversion sequence.
You can parameterize the internal RAM as on-chip memory or register.
The core stores the sample on per slot basis instead of per channel basis. The sample storage core asserts interrupt request (IRQ) when it receives a complete block of samples. You can disable the IRQ assertion during run time. If you disable the IRQ assertion, the software must perform polling method to know when the core receives a complete block of samples.
You can configure the voltage sensor controller through the following methods:
- Configuring voltage sensor controller with Avalon-MM sample storage—to support low performance system.
- Configuring voltage sensor controller with external sample storage—for high performance data streaming.
This configuration mode allows you to use the voltage sensor controller with internal on-chip RAM to store samples. The host sends one command and waits until the storage sends interrupt to read the data. In this configuration mode, the controller captures a block of voltage sample data and stores them inside an on-chip RAM. The host processor retrieves the data before triggering another request.
This configuration mode allows you to use the voltage sensor controller while processing or storing the voltage samples through Avalon-ST samples.
This section describes the interfaces used for the voltage sensor controller core.
The interface type is Avalon-MM slave.
|address||1 or 4||
Avalon-MM address bus. The address bus is in the unit of Word addressing.
|read||1||Avalon-MM read request.|
|write||1||Avalon-MM write request.|
|writedata||32||Avalon-MM write data bus.|
|readdata||32||Avalon-MM read data bus.|
The interface type is Avalon-ST.
|valid||1||Indicates from the source port that current transfer is valid.|
Indicates which channel the voltage sample data is corresponding to for current response.
|data||6||Voltage sample data.|
|startofpacket||1||Indicates from the source port that current transfer is the start of the packet.|
|endofpacket||1||Indicates from the source port that current transfer is the end of the packet.|
The interface type is interrupt.
|Offset||Register Name||Bits||Field||RO/RW||Description||Reset Value|
Determines whether the output data is using calibrated or non-calibrated value.
You must not use this bit to enable calibration.
Unipolar selection for Channel 0 or 1.
Mode select for channel sequencer.
|4:6||CHSEL||RW||Specifies the channel to be converted and used when MD[1:0] = 2'b11.||0x0|
Indicates the controller core's mode of operation.
Do not write to this address when the RUN bit is set. You must wait for the hardware to clear these bits before updating this address.
Control bit to trigger the sequencer core operation.
When the Quartus® Prime software writes a 0 to this address, the controller core completes its current operation and clears this address.
|Offset||Register Name||Bits||Field||RO/RW||Description||Reset Value|
|0x4||0:5||SAMPLE||RO||Values correspond to Slot 0 for Offset 0x0 and Slot 7 for 0x7.||0x0|
Enable bit for end-of-packet interrupt.
Additional information about the document and Altera.
|May 2015||2015.05.04||Initial release.|