This application note provides details on how to design and implement the board management controller using the Intel® MAX® 10 FPGA development kit and the Enpirion® ED810X + FDMF5820 kit.
This design example shows how to use an Intel® MAX® 10 device as a board management controller for the power-up sequencing of a typical system using the PMBus™ interface.
The Intel® MAX® 10 design example uses the following hardware blocks:
- Internal analog-to-digital converter (ADC) and temperature sensor diode (TSD)
- User flash memory (UFM)
- Nios® II soft processor
- Phase-locked loop (PLL)
The design example supports the following features:
- Control the power-up and power-down sequencing of any FPGA using the PMBus-based power modules.
- Monitor power rails of external power modules.
- Data log voltages or temperature conditions that exceed the defined-threshold values.
These values are stored in the
MAX® 10 UFM.
- You can configure the threshold values.
- Control the DC Fan Speed based on the temperature reported by the TSD.
This design example targets the Intel® MAX® 10 FPGA development kit and ED810X+FDMF5820 kit. To enable the Power Management BUS (PMBus™) communication, the Intel® MAX® 10 development kit must be connected to the ED810X+FDMF5820 evaluation kit.
The Intel® MAX® 10 FPGA Development Board does not integrate a DC fan or PMBus-based power module. You need to connect these components through an external hardware. Intel recommends using the Intel Enpirion® Power SoC in this design example.
You can control the speed of the DC fan by varying the duty cycle of the pulse width modulation (PWM).
This design example uses three power modules. Each power module powers different power rails for the Intel® Arria® 10 device.
|Group||Nominal Value (V)||Power Rails on Intel® Arria® 10 Device|
|1||0.9||VCC, VCCP, VCCR_GXB, VCCERAM|
|2||1.8||VCCPT, VCCH_GXB, VCCA_PLL|
Each power group has different threshold and ramp voltage limits. The preset values are defined in the program in main.h. You can update the threshold and ramp voltage via UART using the THRESHOLD or RAMP command.
|Pin||Pin Direction||Location||I/O Standard||Description|
|clk_in||Input||M9||2.5V||Clock input for the whole system.|
|reset||Input||L22||1.5V||Reset the whole design.|
|uart_rx||Input||Y19||2.5V||Receive UART signal to the PC (host).|
|uart_tx||Output||W18||2.5V||Send UART signal from the PC (host).|
|pmbus_alert||Input||E8||3.3-V LVTTL||Alert line for the PMBus.|
|pmbus_alert||Input||D5||3.3-V LVTTL||Alert line for the PMBus.|
|pmbus_alert||Input||B5||3.3-V LVTTL||Alert line for the PMBus.|
|pmbus_scl||Output||C7||3.3-V LVTTL||Clock output to the PMBus devices.|
|pmbus_sda||Bidirectional||C8||3.3-V LVTTL||Bidirectional data line for the PMBus.|
|pmbus_control||Output||A2||3.3-V LVTTL||Control line for the PMBus.|
|pmbus_control||Output||A3||3.3-V LVTTL||Control line for the PMBus.|
|pmbus_control||Output||B4||3.3-V LVTTL||Control line for the PMBus.|
|system_led||Output||T20||1.5V||System indicator for Group 1 power.|
|system_led||Output||U22||1.5V||System indicator for Group 2 power.|
|system_led||Output||U21||1.5V||System indicator for Group 3 power.|
|system_led||Output||AA21||1.5V||System indicator for the UFM storage status.|
|pwm_fan||Output||B7||3.3-V LVTTL||PWM output signal for the DC fan.|
|button_user||Input||M21||1.5V||User button to perform manual power up.|
This design example requires the following software:
- Intel® Quartus® Prime version 15.1.2
- Tera Term
The communication with the Nios® II processor is established through the UART interface. You can use off-the-shelf terminal software such as Tera Term as a user console.
When you set up the Tera Term software, select CR+LF to enable the New-line Transmit option. This ensure the command sent through the terminal is recognized by the controller. You also need to turn on the Local echo option to track the command entered.
Alternatively, you can use the example GUI that is provided with this design example for live data monitoring and display the ADC readout in a graphical format.
The board management controller GUI is developed using TCL. You need to install a TCL interpreter to use the GUI. You can download the installer from the ActiveTCL Downloads. After installing the TCL interpreter, double click the BoardControl.tcl to open the GUI.
|Command Button/ Entry||Description|
|Detect COM PORT||Displays which COM PORT is connected to the PC.|
|Connect COM PORT||Double click the COM PORT to specify which COM PORT to connect. Click the Connect COM PORT to connect the selected COM PORT.|
|Select Channel Radio Button||Specifies which ADC channel that you want to stream the data and displays the data in graphical format.|
|Upper Threshold or Lower Threshold||
Specifies the threshold to be displayed on the graph as red lines. This does not alter the threshold limit for the controller.
If TSD is selected at the Select Channel Radio Button, the upper threshold cannot be more than 100°C while the lower threshold cannot be less than –40°C.
For other selection, the upper threshold cannot be more than 2.5V while the lower threshold cannot be less than 0V.
|Start||Starts streaming the data for the channel selected in the Select Channel Radio Button. The value is displayed and plotted as a graph while the value is transmitted via the UART interface.|
|Stop||Stops data streaming. You can select other channel in the Select Channel Radio Button and update the threshold value.|
|Log File Name||Enter the file name and click Save Datalog if you want to save the output shown in the Interactive Terminal to a file.|
|Clear Terminal Output||Clears the output in the Interactive Terminal.|
To run the GUI or the Tera Term software, you need to connect the UART (J11) to PC. You can manually start the power-up or power-down sequence by using the power-up or power-down button (USER_PB1). In this design example, only three ADC channels are used. You can customize the design if you require more ADC channels for your design. For this board, the maximum analog signal input is up to 2.5V.
This is a customized board consisting of other functions. You can design your own fan board using the design based on the External DC Fan Connections figure.
ED810X+FDMF5820 Kit Setup Instructions
To set up the ED810X+FDMF5820 kit, follow these steps:
- Connect all the jumpers as shown in the ED810X+FDMF5820 Jumper figure.
- Solder 1-kΩ resistors on SDA, SCL, and SMBALERT lines. You are only required to perform this step on the first ED810X+FDMF5820 kit connected in a daisy-chain connection.
- Solder R22 and R23 with the correct resistor value to set the PMBus address for each power module.
- Connect the jumper to J7 as shown in the ED810X+FDMF5820 Jumper figure.
- To set the desired voltage, refer to the FDMF5820 Kit User Guide.
This design example uses the following PMBus address for the power modules.
|Group||Nominal Value (V)||R22(kΩ)||R23(kΩ)||PMBus Address (HEX)|
Custom Fan Board Setup Instructions
To set up the custom fan board, follow these steps:
- Connect J4.4 on the Intel® MAX® 10 Development Kit to point A on the custom fan board. Point A connects to the gate of 2N7000.
- Connect J4.5 on the Intel® MAX® 10 Development Kit to GND on the custom fan board.
- For the 12-V DC-fan connection, connect the red and black lines. You must add a supply line to the fan.
ED810X+FDMF5820 Kit and Intel® MAX® 10 Development Kit Setup Instructions
|Intel® MAX® 10 Development Kit||ED810X+FDMF5820 Kit||Description|
|J4.1||J2.2||Connect the SCL (yellow) to the first ED810X+FDMF5820 Kit.|
|J4.2||J2.4||Connect the SDA (white) to the first ED810X+FDMF5820 Kit.|
|J5.1||J2.6||Connect the SALRT (brown) to the first ED810X+FDMF5820 Kit.|
|J5.2||J2.6||Connect SALRT (red) to the second ED810X+FDMF5820 Kit.|
|J5.3||J2.6||Connect SALRT (grey) to the third ED810X+FDMF5820 Kit.|
|J4.5||J2.1||Connect to GND.|
|First ED810X+FDMF5820 Kit||Second ED810X+FDMF5820 Kit||Third ED810X+FDMF5820 Kit|
|VOUT||Intel® MAX® 10 Development Kit|
|VOUT for the first ED810X+FDMF5820 Kit||J20.1|
|VOUT for the second ED810X+FDMF5820 Kit||J20.3|
|VOUT for the third ED810X+FDMF5820 Kit||J20.5|
To set up the PMBus connections between the Intel® MAX® 10 Development Kit and the ED810X+FDMF5820 Kit, follow these steps:
- Connect the PMBus lines between the Intel® MAX® 10 Development Kit and the ED810X+FDMF5820 Kit.
- Connect the PMBus on each of the ED810X+FDMF5820 Kit in a daisy chain.
For more information, refer to the ED810X+FDMF5820 Kit Daisy-Chain Connections table.
- Connect SCL and SDA lines from the first ED810X+FDMF5820 Kit to the second ED810X+FDMF5820 Kit.
- Repeat this step for the second and third ED810X+FDMF5820 Kit in the daisy chain.
- Connect the VOUT on the ED810X+FDMF5820 Kit to the Intel® MAX® 10 Development Kit (J20 header) to monitor the voltage level of the power module using the Intel® MAX® 10 ADC. For more information, refer to the ED810X+FDMF5820 Kit Connection for VOUT figure and VOUT to J20 Header Connections table.
After you have the complete hardware connection for the design example, you can program the bmc.pdf to the Intel® MAX® 10 device to test the functionality of the design example. If you need to customize the design example, follow the steps listed in the Customizing Design Example section.
To run the design example, follow these steps:
- Connect all the required hardware. For more information, refer to the Hardware Setup Instruction section.
- Download and install the Board Management Controller design example from the design store. For more information, refer to the Importing Design Template section.
- Program the Intel® MAX® 10 device on the Development Kit with bmc.pof located in the project folder.
- Open Tera Term or BoardControl.tcl to send command to the Nios® II processor. For more information, refer to the Other Software section.
Reads the ADC channel voltage or temperature.
Turns on the power groups.
Powers on or off all power groups based on the predefined sequence.
|READ UFM||Reads all the data stored in the UFM.|
|ERASE UFM||Erases all the data stored in the UFM.|
|CHECK SPACE||Checks the available space left in the UFM.|
Updates the upper or lower threshold value for each channel. Data is logged into the UFM when the value detected on each channel is beyond the threshold value.
Updates the threshold value for the ramp-up or ramp-down voltage.
During the power-up operation, the controller checks if the voltages on a power group have reached the threshold value (High) before turning on the next power group. During the power-down operation, the controller checks if the voltages on a power group is below the threshold value (Low) before turning off the power module group.
Updates the lower or upper threshold value for the TSD. Data is logged into the UFM when the temperature detected by the TSD is beyond the threshold value.
This does not impact the fan speed.
|SHOW LIMIT||Shows all limits set in the board management controller.|
|RESET||Resets all limits to the default values defined in main.h.|
Changes the DC fan speed by changing the duty cycle of the PWM.
Enables or disables data log to the UFM.
|SHOW TIMER||Displays the interval to check the ADC or TSD.|
Updates the interval to check the ADC or TSD.
|HELP||Displays the summary of all the supported commands on the terminal.|
Importing Design Template
To import design template, follow these steps:
- Download the design example from Intel Cloud.
- Launch the Intel® Quartus® Prime software. Click the File menu and select New Project Wizard.
- Specify the working directory for your design. Type BMC as the project name. Click Next.
- Select Project template in the Project Type page. Click Next.
- On the Design Templates page, click Install the design templates.
- In the Design Template Installation window, browse to the working directory where the bmc.par file is located. The default destination directory is the location you have specified in Step 3. Next, click OK to install the design template.
- After the installation completes, you will receive a message to prompt you that the design template installation was successful. Click OK.
- On the Design Templates page, select Board Management Controller in the list of available design templates. Click Next.
- On the Summary page, click Finish to complete the Intel® Quartus® Prime project creation.
- On the Tool menu, select Platform Designer .
- In the Open window, select nios.qsys file. Click Open.
- If you encounter error messages on the nios.i2c_opencores_0 and nios.pwm_0, you need to include the <design_folder>/platform/ip folder in the IP search path.
- On the Tools menu, select Options to update the IP search path.
- In the Options window, click Add and browse to the <design_folder>/platform/ip folder. Click Finish.
- You can customize the Platform Designer system to meet your design requirements. Save the changes and generate the HDL.
Importing Software Code for the Nios® II Processor
To import the software code for the design example, follow these steps:
- Unzip the bmc_software.zip in the <project_folder>\software folder.
- Launch the Nios® II Software Build Tools for Eclipse.
- Specify the workspace for the project.
- In the Project Explorer tab, select Import.
- On the Import window, select Import Nios® II Software Build Tools Project. Click Next.
- On the Import Software Build Tools Project window, click Browse to select the <design_folder>/software/bmc folder in the Project location. Type bmc as the Project name. Click Finish.
- On the Importing a custom Software Build Tools project window, click Browse to select the <design_folder>/software/bmc_bsp folder in the Project location. Type bmc_bsp as the Project name. Click Finish.
- In the Project Explorer tab, select the bmc_bsp project. Right-click and select Nios® II and Generate BSP.
- You can edit the C codes in the bmc folder to meet your design requirements. Save the changes.
- On the Project menu, select Build All to compile the changes made on the C codes.
|Nios® II Processor||The soft processor manages the operation of the design. The Nios® II E core is used in this design example.|
Synthesizes the clocks required in this design example.
PLL output counter C0—to synthesize 80-MHz clock for the whole system.
This design example uses a 1-minute timer. By default, the system checks for voltages and temperature at every 5-minutes interval. If the voltage or temperature exceeds the preset limits, the Nios® II processor will data log the value to the UFM.
You can change the timer interval value (TIMER_MINUTE) in main.h. You can also change the timer minute using the UPDATE_TIMER command.
|On-Chip RAM||Storage for the program memory.|
The TSD measures the temperature on the Intel® MAX® 10 device. The presets are defined in main.h. You can also preset on-the-fly using the TEMP command when connected to a PC through the UART.
The fan speed is based on the threshold temperature in the system.
This is a custom Platform Designer component. The duty cycle of the PWM is used to control the fan speed.
For more information about this custom component, refer to the PWM Registers and Setting table.
The default value for the low threshold is 20°C and the high threshold is 50°C.
You can set the threshold value using the TEMP command.
You can change the duty cycle and the PWM frequency in fan.c. When the board is powered on, the fan runs at 33.33% duty cycle. After each timer interrupts, the program reads the TSD temperature and tune the fan to operate at a different speed. You can change the fan speed to 1, 2, or 3 using the FAN command.
|ADC||You can send command to read the voltage and temperature of each channel. There are up to 16 analog inputs that are muxed to the Intel® MAX® 10 ADC. This enables the Intel® MAX® 10 device to monitor multiple voltage rails in the system.|
Storage for data logs—failing channel, failing voltage, or failing temperature. Data is stored based on their failing condition.
Two types of data are stored in UFM1.
Where Y is the failing channel or group, XXX is the 12-bit output data produced by the ADC or TSD block.
LED3 is turned on when UFM1 is full. No new data log will be written into UFM1 when it is full.
When UFM1 is full, you need to read all the UFM1 data to the PC. You can save the readout to a file on the PC for analysis if required. After that, you need to erase the UFM before new data can be logged into the UFM again.
You can also perform some basic functions by using Erase UFM1, Read UFM1, and Check UFM1 Space commands.
The PMBus is built using the OpenCores IP and is used to control the external power module.
The PMBus is a standard protocol used in power management applications. It is built on top of the I2C with additional ALERT and CONTROL lines.
In this design example, the SCL, SDA, and ALERT pins must be pulled to high using a 1-kΩ resistor to run at 400 kHz.
This design example supports the following commands:
You can add new commands in power.c and power.h.
Interactive terminal. The list of supported commands in this design example is listed in the Supported Commands table. You can add your command by modifying main.c.
|Register Name||Size (Bits)||Address (Binary)||Setting||R/W|
|Period||32||0||Specify the PWM period, in clock cycles.||R/W|
|Pulse||32||1||Specify the duration of the high pulse of the PWM, in clock cycles.||R/W|
The following is the flow of the design example:
- During system start up
- Initialize system variable
- Initialize peripheral (ADC, power module, system fan, UFM, timer, and
- Reset to stop the ADC sample
- Power module
- Set the I2C frequency to 400 KHz
- Enable the On/Off control of the power module through PMBus
- Turn off all power module
- Turn off the LED indicator on the development kit
- System fan
- Set the fan speed to medium (50% duty cycle)
- Read the last UFM address data is 0xE0000000
- If true, the UFM content is not erased
- If false, the UFM content will be erased
- When the UFM is clear, it will be showing the full LED indicator
- Enable timer for the voltage and temperature monitor
- Watchdog timer
- The watchdog timer resets the board management controller if it is not responding after 10 seconds during power up or power down
- Initialize system interrupt
- Enable interrupt for the PMBus ALRT line
- Enable interrupt for the button action
- Enable interrupt for the timer
- Enable interrupt for the UART receive
- After the completion of all initialization
- Board management controller turn on the power supplies by power
- Preset voltage for each group:
- Group 1 at 0.9 V
- Group 2 at 1.0 V
- Group 3 at 1.2 V
- Power-up sequence based on the Intel® Stratix® 10 FPGA—Group 1 to Group 2 to Group 3
- Power-down sequence based on the Intel® Stratix® 10 FPGA—Group 3 to Group 2 to Group 1
- Preset voltage for each group:
- Four waiting input:
- Wait for the press button
- Once press button, check if the flag for all power modules is turn on or turn off
- If turn off, proceed to power up the power modules using the power-up sequence
- If turn on, proceed to shut down the power modules using the power-down sequence
- Wait for the timer to trigger voltage and temperature
- Upon reaching the five seconds interval, the board management controller triggers the ADC to check the temperature of the Group 1, Group 2, and Group 3 voltage regulators and the Intel® MAX® 10 FPGA
- Review all three modules to ensure there is no voltage supply that violates the preset voltage
- Any violation of the preset voltage will have data log into the UFM
- Any violation of the preset temperature will have data log
into the UFM
- High temperature preset—50°C
- Low temperature preset—20°C
- System fan
- Fan with PWM duty cycle of 100% if high temperature is detected (50°C)
- Fan with PWM duty cycle of 30% if low temperature is detected (20°C)
- By default, fan with PWM duty cycle of 50%
- Any violation of the preset temperature will have data log into the UFM
- Wait for the user input from the USB
- Preset commands in the firmware—read voltage, set timer, read UFM, delete UFM, and preset threshold voltage
- Each command has an integrated function
- Watchdog timer check
- Wait for the press button
- Board management controller turn on the power supplies by power group
|May 2016||2016.05.02||Initial release.|