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Board Management Controller

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AN-761 | 2016.05.02

Board Management Controller

System Requirements

This example design targets the MAX^® 10 FPGA Development Kit and ED810X+FDMF5820 Kit. To enable PMBus communication, the MAX^® 10 development kit must be connected to the ED810X+FDMF5820 evaluation kit.

Design Example Description

The example design shows how to use a MAX^® 10 device as a board management controller for power-up sequencing of a typical system using the Power Management BUS (PMBus™) interface.

Figure 1. MAX^® 10 Block Diagram

The MAX^® 10 example design uses the following hardware blocks:

Internal analog-to-digital converter (ADC) and temperature sensor diode (TSD)
User flash memory (UFM)
Nios^® II soft processor
Phase-locked loop (PLL)

Supported Features

The design example supports the following features:

Power-up and power-down sequences of the external PMBus-based power modules.
- You can program to support the power-up and power-down sequencing of Altera^® devices.
Monitor power rails of external power modules.
Data log voltages or temperature conditions that exceed the defined-threshold values. These values are stored in the MAX^® 10 UFM.
- You can configure the threshold values.
Control the DC Fan Speed based on the temperature reported by the TSD.

Software Flow

Figure 2. Power Management Controller Software Flow

Pin Assignment and Description

Table 1. Example Design Pin Assignment
Pin	Location	I/O Standard	Description
`clk_in`	M9	2.5V	Clock input for the whole system.
`reset`	L22	1.5V	Reset the whole design.
`uart_rx`	Y19	2.5V	Receive UART signal to the PC (host).
`uart_tx`	W18	2.5V	Send UART signal from the PC (host).
`pmbus_alert[0]`	E8	3.3-V LVTTL	Alert line for the PMBus.
`pmbus_alert[1]`	D5	3.3-V LVTTL	Alert line for the PMBus.
`pmbus_alert[2]`	B5	3.3-V LVTTL	Alert line for the PMBus.
`pmbus_scl`	C7	3.3-V LVTTL	Clock output to the PMBus devices.
`pmbus_sda`	C8	3.3-V LVTTL	Bidirectional data line for the PMBus.
`pmbus_control[0]`	A2	3.3-V LVTTL	Control line for the PMBus.
`pmbus_control[1]`	A3	3.3-V LVTTL	Control line for the PMBus.
`pmbus_control[2]`	B4	3.3-V LVTTL	Control line for the PMBus.
`system_led[0]`	T20	1.5V	System indicator for Group 1 power.
`system_led[1]`	U22	1.5V	System indicator for Group 2 power.
`system_led[2]`	U21	1.5V	System indicator for Group 3 power.
`system_led[3]`	AA21	1.5V	System indicator for the UFM storage status.
`pwm_fan`	B7	3.3-V LVTTL	PWM output signal for the DC fan.
`button_user`	M21	1.5V	User button to perform manual power up.

External Hardware Requirement

The MAX^® 10 FPGA Development Board does not integrate a DC fan or PMBus-based power module. You need to connect these components through an external hardware. Altera recommends using the Altera Enpirion^® Power SoC in this example design.

Figure 3. MAX^® 10 Power Module Connections

You can control the speed of the DC fan by varying the duty cycle of the pulse width modulation (PWM).

Figure 4. External DC Fan Connections

Design in the MAX 10 Device

Figure 5. Qsys System Block Diagram

Table 2. MAX^® 10 Design Components
Block	Description
Nios^® II Processor	The soft processor manages the operation of the design. The Nios^® II E core is used in this example design.
PLL	Synthesizes the clocks required in this example design. PLL output counter C0—to synthesize 80-MHz clock for the whole system.
Timer	This example design uses a 1-minute timer. By default, the system checks for voltages and temperature at every 5-minutes interval. If the voltage or temperature exceeds the preset limits, the Nios^® II processor will data log the value to the UFM. You can change the timer interval value (TIMER_MINUTE) in main.h. You can also change the timer minute using the `UPDATE_TIMER` command.
On-Chip RAM	Storage for the program memory.
TSD	The TSD measures the temperature on the MAX^® 10 device. The presets are defined in main.h. You can also preset on-the-fly using the `TEMP` command when connected to a PC through the UART. The fan speed is based on the threshold temperature in the system.
PWM	This is a custom Qsys component. The duty cycle of the PWM is used to control the fan speed. For more information about this custom component, refer to the PWM Registers and Setting table.
System fan	Temperature < low threshold—the PWM duty cycle is 33%. Low threshold < temperature < upper threshold—the PWM duty cycle is 66.55%. Temperature > upper threshold—the PWM duty cycle is 100%. The default value for the low threshold is 20°C and the high threshold is 50°C. You can set the threshold value using the `TEMP` command. `TEMP L`—trigger point for the low threshold. `TEMP H`—trigger point for the high threshold. You can change the duty cycle and the PWM frequency in fan.c. When the board is powered on, the fan runs at 33.33% duty cycle. After each timer interrupts, the program reads the TSD temperature and tune the fan to operate at a different speed. You can change the fan speed to 1, 2, or 3 using the `FAN` command.
ADC	You can send command to read the voltage and temperature of each channel. There are up to 16 analog inputs that are muxed to the MAX^® 10 ADC. This enables the MAX^® 10 device to monitor multiple voltage rails in the system.
UFM	Storage for data logs—failing channel, failing voltage, or failing temperature. Data is stored based on their failing condition. Two types of data are stored in UFM1. For a failing voltage—0x000AYXXX is logged into the UFM. For a failing temperature—0x00050XXX is logged into the UFM. Where Y is the failing channel or group, XXX is the 12-bit output data produced by the ADC or TSD block. LED3 is turned on when UFM1 is full. No new data log will be written into UFM1 when it is full. When UFM1 is full, you need to read all the UFM1 data to the PC. You can save the readout to a file on the PC for analysis if required. After that, you need to erase the UFM before new data can be logged into the UFM again. You can also perform some basic functions by using `Erase UFM1`, `Read UFM1`, and `Check UFM1 Space` commands.
PMBus	The PMBus is built using the OpenCores IP and is used to control the external power module. The PMBus is a standard protocol used in power management applications. It is built on top of the I2C with additional `ALERT` and `CONTROL` lines. In this design example, the `SCL`, `SDA`, and `ALERT` pins must be pulled to high using a 1-kΩ resistor to run at 400 kHz. This design example supports the following commands: `OPERATION ON`—turns on the power module `OPERATION OFF`—turns off the power module `CONFIG ON`—configures the power module operation by the PMBus only You can add new commands in power.c and power.h.
UART	Interactive terminal. The list of supported commands in this example design is listed in the Supported Commands table. You can add your command by modifying main.c.

Table 3. PWM Registers and Settings. The duty cycle of the PWM is pulse divided by period.
Register Name	Size (Bits)	Address (Binary)	Setting	R/W
Period	32	0	Specify the PWM period, in clock cycles.	R/W
Pulse	32	1	Specify the duration of the high pulse of the PWM, in clock cycles.	R/W

Running the Example Design

To run the example design, follow these steps:

Connect all the required hardware. For more information, refer to the Hardware Setup Instruction section.
Download and install the Board Management Controller example design from the design store. For more information, refer to the Importing Design Template section.
Program the MAX^® 10 device on the Development Kit with bmc.pof located in the project folder.
Open Tera Term or BoardControl.tcl to send command to the Nios^® II processor. For more information, refer to the Other Software section.

Power Module Grouping

This example design uses three power modules. Each power module powers different power rails for the Arria^® 10 device.

Table 4. Power Module Grouping
Group	Nominal Value (V)	Power Rails on Arria^® 10 Device
1	0.9	V_CC, V_CCP, V_{CCR_GXB}, V_CCERAM
2	1.8	V_CCPT, V_{CCH_GXB}, V_{CCA_PLL}
3	1.8	V_CCPGM, V_CCIO

Each power group has different threshold and ramp voltage limits. The preset values are defined in the program in main.h. You can update the threshold and ramp voltage via UART using the THRESHOLD or RAMP command.

Supported Commands

Table 5. Controller Supported Commands. All commands are case sensitive.
Command	Description
`ADC`	Reads the ADC channel voltage or temperature. Example: `ADC ALL`—reads all ADC channels. `ADC 00`—reads ADC Channel 0. `ADC 01`—reads ADC Channel 1. `ADC TSD`—reads temperature.
`POWER`	Turns on the power groups. Example: `POWER 1 ON`—turns on the power for Group 1. `POWER 1 OFF`—turns off the power for Group 1. `POWER 2 ON`—turns on the power for Group 2.
`SEQ`	Powers on or off all power groups based on the predefined sequence. Example: SEQ ON—turns on the power from Group 1 to Group 3 in sequence. SEQ OFF—turns off the power from Group 3 to Group 1 in sequence.
`READ UFM`	Reads all the data stored in the UFM.
`ERASE UFM`	Erases all the data stored in the UFM.
`CHECK SPACE`	Checks the available space left in the UFM.
`THRESHOLD`	Updates the upper or lower threshold value for each channel. Data is logged into the UFM when the value detected on each channel is beyond the threshold value. Example: `THRESHOLD 1 H 1.2`—sets the upper threshold for Channel 1 to 1.2V. `THRESHOLD 1 L 0.95`—sets the lower threshold for Channel 1 to 0.95V. `THRESHOLD 15 H 1.6`—sets the upper threshold for Channel 15 to 1.6V.
`RAMP`	Updates the threshold value for the ramp-up or ramp-down voltage. During the power-up operation, the controller checks if the voltages on a power group have reached the threshold value (High) before turning on the next power group. During the power-down operation, the controller checks if the voltages on a power group is below the threshold value (Low) before turning off the power module group. Example: `RAMP H 1 0.8`—sets the high threshold value to 0.8V for Group 1. `RAMP L 1 0.05`—sets the low threshold value to 0.05V for Group 1.
`TEMP`	Updates the lower or upper threshold value for the TSD. Data is logged into the UFM when the temperature detected by the TSD is beyond the threshold value. This does not impact the fan speed. Example: `TEMP H 80`—sets the high threshold value to 80°C. `TEMP L 20`—sets the low threshold value to 20°C.
`SHOW LIMIT`	Shows all limits set in the board management controller.
`RESET`	Resets all limits to the default values defined in main.h.
`FAN`	Changes the DC fan speed by changing the duty cycle of the PWM. Example: `FAN 1`—changes the fan speed to 1, where the duty cycle is 33.33%. `FAN 3`—changes the fan speed to 3, where the duty cycle is 100%.
`LOG UFM`	Enables or disables data log to the UFM. Example: `LOG UFM ON`—enables data log to the UFM. `LOG UFM OFF`—disables data log to the UFM.
`SHOW TIMER`	Displays the interval to check the ADC or TSD.
`UPDATE TIMER`	Updates the interval to check the ADC or TSD. Example: `UPDATE TIMER 5`—updates the interval to five minutes. The controller checks the ADC or TSD on the interval of every five minutes.
`HELP`	Displays the summary of all the supported commands on the terminal.

Other Software

The communication with the Nios^® II processor is established through the UART interface. You can use off-the-shelf terminal software such as Tera Term as a user console.

When you set up the Tera Term software, select CR+LF to enable the New-line Transmit option. This ensure the command sent through the terminal is recognized by the controller. You also need to turn on the Local echo option to track the command entered.

Figure 6. Setting Up the Tera Term Software

Alternatively, you can use the example GUI that is provided with this design example for live data monitoring and display the ADC readout in a graphical format.

Figure 7. Board Control Management GUI

The board management controller GUI is developed using TCL. You need to install a TCL interpreter to use the GUI. You can download the installer from the ActiveTCL Downloads. After installing the TCL interpreter, double click on the BoardControl.tcl to open the GUI.

Table 6. Functionality of Command Buttons
Command Button/ Entry	Description
Detect COM PORT	Displays which COM PORT is connected to the PC.
Connect COM PORT	Double click the COM PORT to specify which COM PORT to connect. Click the Connect COM PORT to connect the selected COM PORT.
Select Channel Radio Button	Specifies which ADC channel that you want to stream the data and displays the data in graphical format.
Upper Threshold or Lower Threshold	Specifies the threshold to be displayed on the graph as red lines. This does not alter the threshold limit for the controller. If TSD is selected at the Select Channel Radio Button, the upper threshold cannot be more than 100°C while the lower threshold cannot be less than –40°C. For other selection, the upper threshold cannot be more than 2.5V while the lower threshold cannot be less than 0V.
Start	Starts streaming the data for the channel selected in the Select Channel Radio Button. The value is displayed and plotted as a graph while the value is transmitted via the UART interface.
Stop	Stops data streaming. You can select other channel in the Select Channel Radio Button and update the threshold value.
Log File Name	Enter the file name and click Save Datalog if you want to save the output shown in the Interactive Terminal to a file.
Clear Terminal Output	Clears the output in the Interactive Terminal.

Hardware Setup Instructions

MAX 10 Development Kit

Figure 8. MAX^® 10 Development Kit

To run the GUI or the Tera Term software, you need to connect the UART (J11) to PC. You can manually start the power-up or power-down sequence by using the power-up or power-down button (USER_PB1). In this example design, only three ADC channels are used. You can customize the design if you require more ADC channels for your design. For this board, the maximum analog signal input is up to 2.5V.

Custom Fan Board

This is a customized board consisting of other functions. You can design your own fan board using the design based on the External DC Fan Connections figure.

Figure 9. Custom Fan Board

ED810X+FDMF5820 Kit

Figure 10. ED810X+FDMF5820 Kit

Figure 11. ED810X+FDMF5820 Jumper

ED810X+FDMF5820 Kit Setup Instructions

To set up the ED810X+FDMF5820 kit, follow these steps:

Connect all the jumpers as shown in the ED810X+FDMF5820 Jumper figure.
Solder 1-kΩ resistors on SDA, SCL, and SMBALERT lines. You are only required to perform this step on the first ED810X+FDMF5820 kit connected in a daisy-chain connection.
Solder R22 and R23 with the correct resistor value to set the PMBus address for each power module.
Connect the jumper to J7 as shown in the ED810X+FDMF5820 Jumper figure.
To set the desired voltage, refer to the FDMF5820 Kit User Guide.

This example design uses the following PMBus address for the power modules.

Table 7. PMBus Address for Each Power Module. To configure the PMBus address to other values, refer to the device datasheet.
Group	Nominal Value (V)	R22(kΩ)	R23(kΩ)	PMBus Address (HEX)
1	0.9	Short	3.3	0x20
2	1.8	Short	5.6	0x30
3	1.8	Short	Short	0x40

Connection Diagram for the Board Management Controller

Figure 12. Fan Board to the MAX^® 10 Development Kit Connections

Figure 13. Fan Board Power Connections

Custom Fan Board Setup Instructions

To set up the custom fan board, follow these steps:

Connect J4.4 on the MAX^® 10 Development Kit to point A on the custom fan board. Point A connects to the gate of 2N7000.
Connect J4.5 on the MAX^® 10 Development Kit to GND on the custom fan board.
For the 12-V DC-fan connection, connect the red and black lines. You must add a supply line to the fan.

ED810X+FDMF5820 Kit and MAX^® 10 Development Kit Setup Instructions

Table 8. MAX^® 10 Development Kit and ED810X+FDMF5820 Kit PMBus Lines Connections
MAX^® 10 Development Kit	ED810X+FDMF5820 Kit	Description
J4.1	J2.2	Connect the `SCL` (yellow) to the first ED810X+FDMF5820 Kit.
J4.2	J2.4	Connect the `SDA` (white) to the first ED810X+FDMF5820 Kit.
J5.1	J2.6	Connect the `SALRT` (brown) to the first ED810X+FDMF5820 Kit.
J5.2	J2.6	Connect `SALRT` (red) to the second ED810X+FDMF5820 Kit.
J5.3	J2.6	Connect `SALRT` (grey) to the third ED810X+FDMF5820 Kit.
J4.5	J2.1	Connect to `GND`.
J4.11	J2.2
J5.5	J2.3

Figure 14. PMBus Connection on the ED810X+FDMF5820 Kit

Figure 15. PMBus Connection from the MAX^® 10 Development Kit to the First ED810X+FDMF5820 Kit

Table 9. ED810X+FDMF5820 Kit Daisy-Chain Connections
First ED810X+FDMF5820 Kit	Second ED810X+FDMF5820 Kit	Third ED810X+FDMF5820 Kit
J2.2	J2.2	J2.2
J2.4	J2.4	J2.4

Figure 16. ED810X+FDMF5820 Kit Connection for VOUT

Table 10. VOUT to J20 Header Connections
VOUT	MAX^® 10 Development Kit
VOUT for the first ED810X+FDMF5820 Kit	J20.1
VOUT for the second ED810X+FDMF5820 Kit	J20.3
VOUT for the third ED810X+FDMF5820 Kit	J20.5

To set up the PMBus connections between the MAX^® 10 Development Kit and the ED810X+FDMF5820 Kit, follow these steps:

Connect the PMBus lines between the MAX^® 10 Development Kit and the ED810X+FDMF5820 Kit.
Connect the PMBus on each of the ED810X+FDMF5820 Kit in a daisy chain. For more information, refer to the ED810X+FDMF5820 Kit Daisy-Chain Connections table.
1. Connect SCL and SDA lines from the first ED810X+FDMF5820 Kit to the second ED810X+FDMF5820 Kit.
2. Repeat this step for the second and third ED810X+FDMF5820 Kit in the daisy chain.
Connect the VOUT on the ED810X+FDMF5820 Kit to the MAX^® 10 Development Kit (J20 header) to monitor the voltage level of the power module using the MAX^® 10 ADC. For more information, refer to the ED810X+FDMF5820 Kit Connection for VOUT figure and VOUT to J20 Header Connections table.

CAUTION:

The analog channel of the MAX^® 10 development kit supports up to 2.5V only. Do not provide voltage higher than 2.5V to the analog channel.

Figure 17. MAX^® 10 Development Kit Connection for the ADC Input Port. You can modify the example design if you are using more than three power modules in your design. There are up to 16 ADC channels available.

After you have the complete hardware connection for the example design, you can program the bmc.pdf to the MAX^® 10 device to test the functionality of the example design. If you need to customize the example design, follow the steps listed in the Customizing Example Design section.

Figure 18. Example Design Complete Hardware Connections

Customizing the Example Design

To customize the example design to meet your requirements, follow the steps listed in the Importing Design Template and Importing Software Code for the Nios^® II Processor sections.

Importing Design Template

To import design template, follow these steps:

Download the design example from Altera Cloud.
Launch the Quartus^® Prime software. Click on the File menu and select New Project Wizard.
Specify the working directory for your design. Type BMC as the project name. Click Next.
Select Project template in the Project Type page. Click Next.
On the Design Templates page, click on Install the design templates.
In the Design Template Installation window, browse to the working directory where the bmc.par file is located. The default destination directory is the location you have specified in Step 3. Next, click OK to install the design template.
After the installation completes, you will receive a message to prompt you that the design template installation was successful. Click OK.
On the Design Templates page, select Board Management Controller in the list of available design templates. Click Next.
On the Summary page, click Finish to complete the Quartus^® Prime project creation.
On the Tool menu, select Qsys.
In the Open window, select nios.qsys file. Click Open.
If you encounter error messages on the nios.i2c_opencores_0 and nios.pwm_0, you need to include the <design_folder>/platform/ip folder in the IP search path.
On the Tools menu, select Options to update the IP search path.
In the Options window, click Add and browse to the <design_folder>/platform/ip folder. Click Finish.
You can customize the Qsys system to meet your design requirements. Save the changes and generate the HDL.

Importing Software Code for the Nios^® II Processor

To import the software code for the example design, follow these steps:

Unzip the bmc_software.zip in the <project_folder>\software folder.
Launch the Nios^® II Software Build Tools for Eclipse.
Specify the workspace for the project.
In the Project Explorer tab, select Import.
On the Import window, select Import Nios^® II Software Build Tools Project. Click Next.
On the Import Software Build Tools Project window, click Browse to select the <design_folder>/software/bmc folder in the Project location. Type bmc as the Project name. Click Finish.
On the Importing a custom Software Build Tools project window, click Browse to select the <design_folder>/software/bmc_bsp folder in the Project location. Type bmc_bsp as the Project name. Click Finish.
In the Project Explorer tab, select the bmc_bsp project. Right-click and select Nios^® II and Generate BSP.
You can edit the C codes in the bmc folder to meet your design requirements. Save the changes.
On the Project menu, select Build All to compile the changes made on the C codes.

Document Revision History

Table 11. Document Revision History
Date	Version	Changes
May 2016	2016.05.02	Initial release.

Popular Links:

Board Management Controller

Board Management Controller

System Requirements

Design Example Description

Supported Features

Software Flow

Pin Assignment and Description

External Hardware Requirement

Design in the MAX 10 Device

Running the Example Design

Power Module Grouping

Supported Commands

Other Software

Hardware Setup Instructions

MAX 10 Development Kit

Custom Fan Board

ED810X+FDMF5820 Kit

ED810X+FDMF5820 Kit Setup Instructions

Connection Diagram for the Board Management Controller

Custom Fan Board Setup Instructions

ED810X+FDMF5820 Kit and MAX^® 10 Development Kit Setup Instructions

Customizing the Example Design

Importing Design Template

Importing Software Code for the Nios^® II Processor

Document Revision History

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ED810X+FDMF5820 Kit Setup Instructions

Custom Fan Board Setup Instructions

ED810X+FDMF5820 Kit and MAX® 10 Development Kit Setup Instructions

Importing Design Template

Importing Software Code for the Nios® II Processor

ED810X+FDMF5820 Kit and MAX^® 10 Development Kit Setup Instructions

Importing Software Code for the Nios^® II Processor