TI wideband ADC12DJ3200 device is the 12-bit converter which is capable of operating at up to 3.2 gigasamples per second (Gsps) in dual channel mode or 6.4 Gsps in an interleaved single channel mode. This design is programmed to run at the fastest sample rate of 6.4 Gsps in single channel mode, where this mode effectively interleaves the two analog-to-digital converter (ADC) channels together to form a single channel ADC at twice the sampling rate.
Applications such as high-density phased array radar, satellite communications, 5G systems, and medical imaging are driving the need for increased data throughput, higher bandwidth, and lower power. Small package size and lower PCB cost are preferred in these applications.
This reference design provides the following key features:
- Two 8-lane simplex RX JESD204B IP cores interoperate with the ADC12DJ3200
EVM through the
Stratix® 10 Transceiver Signal Integrity
Development Kit FMC+ port A running at 6.4 Gbps per lane. The
JESD204B IP core has the following parameters:
- The LMK04828 clock generator on the ADC12DJ3200 EVM provides 160 MHz for I/O PLL core reference clock and 160 MHz for transceiver CDR reference clock. These clocks are transmitted from a single clock chip through the FMC+ port A to the core reference clock pin and the dedicated transceiver pin at the FPGA. The LMK04828 also provides a clock to LMX2582, where the LMX2582 synthesizer generates a 3,200 MHz ADC sampling clock.
- The I/O PLL on the FPGA generates link clock and frame clock. The IP cores, RX transport layers, and deterministic latency measurement block are sourced from link clock. The frame clock is supplied to RX transport layers, test pattern checkers, and any application layer.
- The LMK04828 clock chip generates continuous SYSREF signal for the RX JESD204B IP cores at the FPGA and the ADC12DJ3200 device.
- The deterministic latency measurement block measures the number of link clock counts between the start of combined SYNC_N deassertion output from the two JESD204B IP cores to the first user data output to ensure latency is deterministic.
- Frequency Checker monitors to ensure the I/O PLL core reference clock and transceiver CDR reference clock from the EVM clock generator and RX recovered clock frequency generated from CDR are correct.
- The main.tcl script (located at the <project directory>/system_console directory) generated from the JESD204B Example Design (LMF=888, 6.144 Gbps) (Stratix 10 only) preset is enhanced to support multi-link design. Refer to the Procedures in the main.tcl System Console Script table for details about the .tcl procedures.
- A Signal Tap II file is included in this design for debug assistance, such as monitoring the short transport pattern at RX transport layers, checking correct octet ramp pattern at the output of the JESD204B IP cores, and checking the output counter to ensure design is deterministic from one power cycle to another.
The top-level HDL files of this reference design instantiate the following submodules:
- Top level Platform Designer system
- JESD204B subsystem includes reset sequencer, two ×8-lane RX JESD204B IP cores, transceiver PHY reset controller, and Avalon® Memory-Mapped (Avalon-MM) pipeline bridge.
- JTAG-to- Avalon® master bridge for the System Console.
- Link clock and frame clock generated by the core PLL.
- Serial peripheral interface (SPI) master—Optional component in this design. You can use this component in your custom design if needed.
- RX transport layers for link 0 and link 1
- Test pattern checker
Note: This test pattern checker is an optional module for this design example and is not suitable to test the ramp pattern transmitted from the ADC12DJ3200 device.
- Deterministic latency measurement
- Frequency checker
The reference design requires the following hardware tools:
- Intel® Stratix® 10 Transceiver Signal Integrity Development Kit (1SG280HU2F50E2VGS1).
- TI ADC12DJ3200 Evaluation Module—This design is tested in TI ADC12DJ3200 EVM Rev E3.
- Micro-USB cable and power adaptor—Part of Intel® Stratix® 10 Transceiver Signal Integrity Development Kit accessories.
- Mini-USB cable and power cable—Part of ADC12DJ3200 EVM accessories.
The reference design requires the following software:
- Intel® Quartus® Prime Pro Edition version 17.1.
- TI ADC12DJXX00 Configuration GUI Software that is compatible with ADC12DJ3200 EVM Rev E3.
- Future Technology Devices International (FTDI) Combined Driver Model (CDM) driver package—D2XX driver.
Set the following MSEL DIP switches to the "1" position to
enable JTAG Only Mode.
- SW11: MSEL0 =1
- SW10: MSEL1 =1
- SW10: MSEL2=1
- Set the SW3-2 to the ON position to disable MAX® V devices in the JTAG chain.
- Set the remaining DIP switches to the factory default settings. Refer to the Factory Default Switch Settings table in the Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide.
Slot the ADC12DJ3200 EVM module into FMC+ port A on the
Stratix® 10 Transceiver Signal Integrity
Ensure the board-to-board FMC+ connection is secure.
- Connect the micro-USB cable and power adaptor to the Intel® Stratix® 10 Transceiver Signal Integrity Development Kit.
- Connect the mini-USB cable and power cable to the ADC12DJ3200 EVM module.
To run the reference design, follow these steps:
- Compile the project to include Signal Tap II file.
- Set up the TI ADC12DJxx00 GUI software and board.
- Configure the FPGA.
- Check the basic operation.
- Execute the Tcl Script File (.tcl) code and initialize the JESD204B links.
- Check for deterministic latency.
The reference design provided does not enable Signal Tap II Logic Analyzer in the Intel® Quartus® Prime project.
To compile the design that include the Signal Tap II file (.stp) into the Intel® Quartus® Prime project, follow these steps:
- To test the reference design targeted for Intel® Stratix® 10 GX device, download the reference design file to your local project directory.
- Launch the Intel® Quartus® Prime Pro Edition software.
- To prepare the design template in the Intel® Quartus® Prime Pro Edition software GUI, click File > Open and change the file type to the Quartus Prime Design Template File (*.par). Browse to the <project>.par file and click Ok.
- Turn on Assignments > Settings > Category > Enable Signal Tap II Logic Analyzer.
- Browse to the stp1.stp file located at the /stp directory and click Ok.
- To compile the project, select Processing > Start Compilation.
- Install the ADC12DJ3200 GUI Configuration software.
- Extract the files from the .zip file.
- Run the executable file (setup.exe) and follow the instructions. Use the default installation location (C:\Program Files (x86)\Texas Instruments\ADC12DJxx00 GUI\).
Connect the USB cable to PC and turn on the power supply for
the ADC12DJ3200 EVM. Launch the ADC12DJ3200 GUI.exe available from your installation directory.
The USB status becomes green if the ADC12DJ3200 EVM card is detected.Figure 3. ADC12DJxx00 GUI EVM Tab
Replace the original files with the following modified version
of the .cfg files using the same file
- Select Clock Source > On-board. This is the default setting.
- Select On-board Fclk Selection > Fclk = 3200 MHz.
- Select Decimation and Serial Data Mode > JMODE1.
Click Program Clocks and ADC.
Clicking the Program Clocks and ADC overwrites any previous device register settings.
Verify the settings for ADC12DJxx00 LMK04828 > Clock Outputs tab as in the following figure.
Figure 4. ADC12DJxx00 GUI LMK04828 Tab
Before configuring the FPGA, ensure the following:
- The Intel® FPGA Download Cable II driver is installed on the host computer.
- The Intel® Stratix® 10 Transceiver Signal Integrity Development Kit is powered on.
- No other running application is using the JTAG chain.
- In the Intel® Quartus® Prime Programmer, select Hardware Setup > Stratix 10H SI Dev Kit[USB-1].
- Click Auto Detect to display the devices in the JTAG chain. Select device 1SG280HU2S1.
- Right click and select Change File. Choose the appropriate SRAM Object File (.sof) from the <project directory>/output_files directory. Click Open.
- Turn on Program/Configure for the .sof file.
- Click Start to program the image into the FPGA.
Make sure the I/O PLL core reference clock (refclk_core), transceiver clock data recovery (CDR)
reference clock (refclk_xcvr), and receiver
(RX) recovered clock (rxphy_clk) are 160
The LMK04828 clock generator from the ADC12DJ3200 EVM module provides the reference clock to I/O PLL and transceiver CDR. A frequency checker module is added to this reference design to verify the I/O PLL core reference clock, transceiver CDR reference clock, and RX recovered clock frequency are correct. You can view the measured clock frequency in the Signal Tap II file by clicking at the freq_chk instance as indicated in the following figure. The frequency values of all measured clocks are displayed in Hz after running analysis or autorun analysis.Figure 6. Measured Reference Clock and Recovered Clock Frequencies
Verify the RX PHY status by monitoring the status of
and rx_cal_busy[7:0] signals for link 0 and link 1.
These signals are available under rx_phy instance in the Signal Tap II file.
Table 1. Bits for Each Lane for Normal Operation of the JESD204B RX Paths Signal Bit rx_is_lockedtodata 1 rx_analogreset 0 rx_digitalreset 0 rx_cal_busy 0Figure 7. RX PHY Status
- Launch the System Console in the Intel® Quartus® Prime software, click Tools > System Debugging Tools > System Console.
In the Tcl Console, type the
- cd—To change the directory to the working directory that contains the main.tcl script (located at <project directory>/system_console)
- source main.tcl—To execute the main.tcl script.
- start_basic_test—To execute the start_basic_test procedure.
- Restart the converter and reprogram the clocks and ADC.
- Restart and reconfigure the FPGA.
- Execute the .tcl code to initialize the JESD204B links.
- Read the RX Buffer Delay (RBD) count by typing the read_rx_status0 procedure in the Tcl Console and record the value. The RBD count is from the csr_rbd_count field in the rx_status0[10:3] register (at offset 0x80).
- Measure and record the number of link counts between the start of combined SYNC_N deassertion output from the two JESD204B IP cores to the first user data output, which is the assertion of the jesd204_rx_link_valid signal. Ensure the latency is constant for every converter and FPGA power cycle.
- Repeat step 1 to step 5 for a few times.
Example of the System Console output after executing the read_rx_status0 procedure:
% read_rx_status0 master_list_length = 1 RX Status0 (Link 0)= 0x00000009 RX Status0 (Link 1)= 0x00000009
RX Status0 = 0x00000009 indicates the following conditions:
- bit=1, JESD204B link is out of synchronization (SYNC_n deasserted).
- bit=1, csr_rbd_count = 1
For detailed description of the csr_rbd_count field of the rx_status0[10:3] register (at offset 0x80), refer to the Addressmap Information for 'altera_jesd204_rx_regmap'.
When the link up is successful, you should observe the following conditions:
- USER_LED0–USER_LED3 (D12–D15) illuminate
- USER_LED4 (D16) turned off
|On-board User LED||Signal||Indication when LED Illuminates|
|LED D12||rx_frame_rst_n||The transport layers and test pattern checkers are out of reset.|
|LED D13||rx_link_rst_n||The IP cores, transport layers, and deterministic latency module are out of reset.|
|LED D14||alldev_lane_aligned||All lanes are aligned for two JESD204B IP cores receiver.|
|LED D15||rx_dev_sync_n_out||The receivers at link 0 and link 1 have successful received K28.5 characters.|
|LED D16||rx_link_error||The interrupt is triggered at any of the JESD204B RX IP cores.|
JESD204B block in the ADC12DJ3200 device defines the short transport test pattern for N’=12 test mode to verify that the transport layer test patterns in transmitter and receiver are operating correctly.
To verify the short transport test patterns at the receiver transport layers of the FPGA, follow these steps:
- In the Intel® Quartus® Prime Pro Edition software, click Tools > Signal Tap II Logic Analyzer.
- Check the JTAG chain configuration. Select the hardware and device correctly.
- In the Instance Manager, click rx_tprt > run Analysis/Autorun Analysis.
Ensure both link 0 and link 1 of receiver output transport layers are matched with the following table.
|8 lanes of link 0||DA0||0xF01||0xF02||0xF03||0xF04||0xF05||T|
|8 lanes of link 1||DB0||0xF01||0xF02||0xF03||0xF04||0xF05||T|
You can run the ramp test mode after running the short transport pattern test. In this mode, the JESD04B link layers operate normally, but the transport layers are disabled. After the initial lane alignment sequence (ILAS), each lane transmits an identical octet stream that increments from 0x00 to 0xFF and repeats.
To verify the ramp pattern at output data of DLL to the input receiver transport layer, follow these steps:
- Change the command in line 7 of the ADC12DJxx00_JMODE1.cfg file to: 0x0205 0x04 // Set JTEST to 4 gives ramp test mode.
- Reprogram the clocks and ADC.
- Reconfigure the FPGA.
- Type the start_basic_test procedure in the System Console Tcl Console to execute the .tcl script to initialize the JESD204B links.
- In the Instance Manager, click rx_link > run Analysis.
- If you want to check the JESD204B link up process, set a trigger condition to the dev_sync_n signal. The signal tap waits for trigger condition to occur. The trigger condition should occur once you execute the start_basic_test procedure.
A system is deterministic if latency is repeatable from power-up cycle to power-up cycle. In this design, the JESD204B IP cores are configured as subclass 1 mode to support deterministic latency. The TI ADC12DJ3200 EVM uses AC coupling for SYSREF+/- , thus the periodic SYSREF signal is required to achieve deterministic latency. The SYSREF period from LMK04828 is configured to run at a frequency equals to the Local Multi-Frame Clock (LMFC) frequency before the SYSREF signal is supplied to the ADC and FPGA. The SYSREF pulse restarts the LMFC counter on the JESD204B IP cores and converter device, and realigns the LMFC counter to the LMFC boundary.
To ensure the deterministic latency in the reference design, follow these steps:
Check the FPGA SYSREF single detection.
For detailed description of the registers in the JESD204B RX IP core, refer to the Addressmap Information for 'altera_jesd204_rx_regmap'.Passing criteria: The value of csr_sysref_singledet and csr_sysref_lmfc_err should be zero.Figure 12. csr_sysref_singledet and csr_sysref_lmfc_err Observed from the .tcl Console
Check the SYSREF captured.
Passing criteria: If the SYSREF is sampled correctly, the LMFC counter should be reset. Thus, the RBD_count value should only drift within 1–2 link clocks from one power cycle to another power cycle. In this test, the RBD_count is consistently 1 across 5 power cycle tests. It means the /R/ character is consistently received at 1 LMFC count before the next LMFC boundary for 5 power cycle tests.Figure 13. Early RBD Release Opportunity for Latest Arrival Lane Within One LMFC
Check the latency from the start of combined SYNC_N deassertion output from the two JESD204B IP
cores to the first user data output.
Passing criteria: You should observe consistent latency from the start of combined SYNC_n deassertion to the assertion of the jesd204_rx_link_valid signal. In this design test, you should consistently observe 67 link cycles clock from one power cycle to another.Figure 14. Measured Latency from the Start of Combined SYNC_n to the First User Data Output
Ensure the data latency is fixed during user data phase.
Passing criteria: The ramp pattern should be in perfect shape with no distortion.Figure 15. Ramp Pattern in Perfect Shape
You need to regenerate the platform designer system if you want to modify the system, such as IP components settings and interfaces.
To regenerate the HDL files for the top level platform designer system, follow these steps:
- Open altera_jesd204_ed_qsys_RX.qsys.
In the platform designer GUI, click Generate > Generate HDL.
Note: If you want to modify the JESD204B IP cores, Transceiver PHY Reset Controller, and other component settings, right click on the altera_jesd204_subsystem_RX component and select Drill into Subsystem. After the modification, save the system. Go back to the top level platform designer system file and generate the HDL files.
- To rerun design in hardware, follow the steps in the Running the Reference Design section.
|start_basic_test||—||Main procedure that performs global reset, set checker test mode, enable SYSREF continuous detection mode, clear JESD204B IP cores error status registers, and report link status.|
|reset||—||Perform global reset.|
0: Deassert link and frame reset.
1: Assert and hold link and frame reset.
Note: Link and frame clock domains should be held in reset while writing to the JESD204B IP control and status register (CSR).
|set_testmode||alt, ramp, prbs||
alt: Set pattern checker to alternate pattern.
ramp: Set pattern checker to ramp pattern.
prbs: Set pattern checker to pseudo-random binary sequence (PRBS) pattern.
|sysref_con||—||Enable SYSREF continuous detection with SYSREF single detection.|
|rbd_offset||integer||Adjust RBD offset value to eliminate RX lane deskew error if needed. Refer to the JESD204B IP Core User Guide for more details.|
Read the status of the parallel I/O (PIO) registers. The PIO status has the following configurations:
Note: Use the read_err_status procedure to report error in description.
|read_err_status||—||Read the JESD204B IP error status registers. For detailed description of the status registers, refer to the Addressmap Information for 'altera_jesd204_rx_regmap'.|
|clear_err_status||—||Clear the JESD204B IP error status registers.|
|read_rx_status0||—||Read JESD204B IP rx_status0 register. For detailed description of the status registers, refer to the Addressmap Information for 'altera_jesd204_rx_regmap'.|
|wait_seconds||integer||Set to wait for integer seconds.|
|eval_test||—||Report the link status.|
|December 2017||2017.12.19||Initial release.|