ISDF16 San Francisco Keynote

ISDF Keynote by CEO Brian Krzanich - Part 1

Hear about the evolution and transformation of the smart and connected world and the importance of SoC FPGAs. See live demos of SoC FPGAs in action. Guest speaker Prith Banerjee from Schneider Electric.

ISDF Keynote by CEO Brian Krzanich - Part 2

Hear about the evolution and transformation of the smart and connected world and the importance of SoC FPGAs.  See live demos of SoC FPGAs in action.  Guest speaker Prith Banerjee from Schneider Electric.

ISDF Keynote by CEO Brian Krzanich - Part 3

Hear about the evolution and transformation of the smart and connected world and the importance of SoC FPGAs.  See live demos of SoC FPGAs in action.  Guest speaker Prith Banerjee from Schneider Electric.

Software Sessions

Configurable Embedded Systems using SoC FPGA Multi-Core Architectures

This session analyzes system software architecture trends and technologies for integrated processor and field-programmable gate array (FPGA) systems. We will focus on using embedded Linux, real-time operating systems, and bare-metal programming for single-core, symmetric multiprocessing (SMP), and asymmetric multi-core (AMP) multi-core configurations.

  • Bare-metal and embedded operating system options
  • SMP/AMP multi-core software architectures
  • Virtualization and hypervisors including Kernel-based Virtual Machine (KVM)

Victoria Mitchell, Intel Programmable Solutions Group

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Heterogeneous Multicore OpenAMP

There is a significant and growing trend  toward heterogeneous multicore systems which promise increased system performance while still conforming to tight power budgets. For example, Altera SoC FPGA systems typically combine a hard dual-core ARM Cortex-A9 processor with any number of Nios II soft processors in the FPGA fabric. Running multiple operating systems in systems like these creates new and interesting challenges for system architects. This session will present the OpenAMP standard, opportunities it provides for system partitioning and consolidation, typical use cases, and design considerations for architecting and developing software on multicore systems.

 

Felix Baum, Mentor Graphics

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Virtual Prototyping for Intel® SoC FPGA-based Hardware and Software Development

This session will overview the effective approach of Virtual Platforms and explain how many of the problems that occur when using physical hardware are solved: full visibility, powerful control, and non-intrusive trace analysis to create a deterministic and scalable environment. With this approach, issues in the system can be found earlier in the design lifecycle and resolved.

 

Joe Hamman, Mentor Graphics

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Lessons from the Spaceship for the Sedan

In order for autonomous driving to become mainstream, a vehicle must intelligently gather relevant data and communicate not only within its own complex vehicle systems but with the external world. In particular, advanced driver assistance systems (ADAS) must rely on reliable automotive application software on image recognition SoC platforms in order to accurately capture necessary information to make autonomous driving-related decisions. We'll examine the intricacies of autonomous driving, especially around technologies to ensure safety, that must be addressed in order to bring it to the real world.  

 

Daniel Noal, Wind River Systems

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Customizable Graphics Acceleration

Today's platforms have graphics requirements for modern, smartphone-like HMIs and enabling frameworks like Qt*, WebGL* and Android*. This presentation reviews those requirements, including a comparison of Open GL ES 2.0 and 3.1.  It then introduces a complete Qt 5.x system solution for Altera Cyclone V SoCs using a fully OpenGL ES 2.0/3.1 and VULKAN* compliant graphics rendering core and explains how to install and integrate it.

Thomas Hase, TES

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Wireless Workload Acceleration using SoC FPGAs

Offloading key portions of the algorithm to the FPGA and the use of hardened floating-point DSP blocks can deliver significantly improved performance.  This session will examine the implementation of wireless remote radio head (RRH) digital pre-distortion (DPD) algorithm acceleration using FPGA hardware acceleration and the peformance improvement, power and space savings of using these techniques.

 

Xiaohan Chen, Intel PSG Wireless Business Division

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Technologies for Securing Intel® SoC FPGAs using an Embedded Linux* System

This presentation will discuss the need for security, including common hacks and new attack vectors, and how to protect against them when using an embedded Linux system.  Building in security using root of trust and integrity management will be examined. Remote attestation in Network Functions Virtualization (NFV) system clusters and signed over-the-air (OTA) updates in IoT use cases are provided to illustrate protective measures.

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Building Secure, Connected, RTOS-based IoT Devices

Real-time Operating System (RTOS) devices have always played a critical role when strict performance and reliability requirements were necessary. In today’s connected world with a rapidly growing base of IoT devices, the need for security, safety certification, scalability and virtualization is expanding from optional requirements needed by select industries to a mandatory requirement of all industries when creating next-generation devices. Learn how to fulfil these requirements for today’s intelligent and connected devices.

Michel Chabroux, Wind River

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Power Efficient Acceleration using Intel SoC FPGAs

This presentation talks about parallel processing using OpenCL*provides performance improvement with power efficiency and Convolutional Neural Network (CNN) application examples.

Bill Jenkins, Intel Programmable Solutions Group

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Targeting SDR Systems to hardware using SoC FPGA boards with Model-based Design

Case study featuring a workflow based on MATLAB* and Simulink* for development of software-defined radio (SDR) algorithms. The workflow enables teams to use SDR hardware based on Intel SoC FPGAs and Analog Devices RF transceivers.

Eric Cigan, MathWorks

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SoC FPGA Secure Boot Software Track

SoC FPGA Secure Boot

This presentation discusses the secure boot environments provided by the Cyclone® V SoC FPGA device family and the Arria® 10 SoC FPGA device family. Reviews the standard boot flow and secure boot flows that are available in each family as well as the development tools that provide access and enable these capabilities.

Rodney Frazer, Intel Programmable Solutions Group

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Linux* Case Study: Options for Low-Latency and Real-Time Behavior

SoC FPGAs can offload the processor by accelerating specific workloads, and have the flexibility to adapt to changing interface standards.  This session will examine application examples for accelerating software using FPGA hardware.

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Combination of Intel® FPGA SDK for OpenCL* Kernel with Video IP Cores

The Intel PSG SDK for Open Computing Language (OpenCL) allows a developer to abstract away the traditional hardware FPGA development flow and use a much faster and higher level software development flow for development of FPGA based hardware modules. We will describe an implementation of a Mandelbrot algorithm acceleration module, developed in OpenCL, combined with a multi-resolution video display based on the Intel PSG Video and Image Processing Suite. We will present the tools and methodology required to create the OpenCL Kernel and video processing system, including the integration of Video Processing modules to the OpenCL Kernel and the development of an OS video driver to configure the Clocked Video Output and Reconfigurable PLL to enable video outputs of different resolutions.

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Interfacing to WLAN Networks with Intel SoC FPGAs

This presentation describes the hardware configuration to boot Linux* from the SD controller on the HPS side while using a soft SDIO controller in the FPGA to connect to a TI WL1835MOD WLAN module. It explains the usage of Altera’s device tree flow and additional FPGA peripherals for receiving interrupts from and controlling power to the WLAN module.

The software section highlights the usage of standard Linux SDHCI and WL18XX drivers for quickly implementing a working system. Using the wired Ethernet connection of the development kit, together with the OPKG Package Manager in the Ångström Linux distribution, it is just a manner of minutes to add the necessary WLAN tools to the root filesystem of the GSRD.

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Hardware Sessions

Enabling the IoT Vision pt.1

Enabling the IoT Vision pt.2

Enabling the IoT Vision pt.3

Enabling the IoT Vision: Data Center to Edge

Part 1 Smart and Connected World

Part 2 Across the Network

Part 3 Enabling the IoT

Hardware and software developers are facing an ever-changing, connected world.  Intel is uniquely positioned to support developers with a portfolio of heterogeneous solutions that span across the data center, network infrastructure and Internet of Things (IoT).  This session will provide a comprehensive vision of how the combination of Intel FPGA and processor connects the world from the sensor to the data center and back.

  • Heterogeneous solutions with end-to-end span
  • Data center acceleration
  • Networking and access acceleration
  • IoT acceleration and connectivity
Ian Land, Intel Data Center Group
Mike Fitton, Intel Programmagle Solutions Group Wireless Business Divtion
Joerg Bertholdt, Intel Programmable Solutions Group Industrial Business Division
Watch Part 1
PDF Part 1
Watch Part 2
PDF Part 2
Watch Part 3
PDF Part 3

SoC FPGA Hardware Security Requirements and Roadmap

This presentation sets forth a taxonomy of security threats for FPGA and SoC FPGA end markets, then examines the Intel® SoC FPGA security feature roadmap to help protect against these threats.

Ryan Kenny, Intel Programmable Solutions Group

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SoC FPGA Secure Boot

This presentation discusses the secure boot hardware capabilities of the Cyclone® V SoC device and the Arria® 10 SoC device.  It then discusses the typical boot model of Cyclone V SoC and then how it can be secured by leveraging the FPGA fabric on the device.  Lastly, it will discuss the additional hardware facilities provided by the Arria 10 SoC devices.

Rodney Frazer, Intel Programmable Solutions Group

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Hardware-Software Partitioning in SoC FPGAs: Enhancing Real-Time Performance

When acceleration is discussed in the context of processors, this usually refers to increasing metrics of computations per second or computational throughput.  However, when dealing with real-time systems, latency and determinism are often more critical metrics, and custom hardware can be used to speed up response time and decrease system “jitter.”   This presentation discusses the methods and advantages of separating latency critical functions through a hardware/software partitioning case study of Industrial Ethernet. 

 

Guy Irving, Macnica Americas

 
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Optimizing e.MMC Memory on Intel® SoC FPGA Platforms

Managed NAND devices, like e.MMC, provide not only industry standard features and characteristics but also detailed proprietary features for monitoring health status. Though these managed NAND devices are designed to be as drop-in ready as possible, many of its features are often under-utilized.  With a little investment in software design, significant performance and data reliability improvements can be made.  This presentation will cover the best practice methods on how to optimize data throughput, improve data reliability, and increase life span capabilities of the e.MMC memory on Altera SoC platforms.

Justin Hunter, Micron Technology

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Industrial IoT motor control trajectory optimization

Performance of servomotor-based machines is generally compromised due to poorly chosen motion trajectories and this problem is compounded when multiple axes of motors must be coordinated. The correct trajectories are cumbersome to generate and burdensome to evaluate in real-time, but these are not issues for SoC FPGAs; half of the problem is well-suited to a processor while the other half suits FPGA hardware.  Once a sophisticated trajectory generator is integrated, communication bandwidth between distributed controllers is reduced and synchronization and coordination is aptly done over pervasive, secure wireless or wired Ethernet networks.  This presentation describes such a trajectory generator solution.

Randall Restle, Digi-Key

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Flying with Intel® SoC FPGA: Smart Drones Enabled by Open Source Platform

The future of unmanned aerial vehicle (UAV) platforms is expanding, requiring faster processor speeds and flexible architectures while also providing more inputs and outputs to support additional hardware modules and sensors. This presents many challenges in today’s UAV market, because most of the platforms are designed based on the traditional micro-controller unit (MCU)due to its low cost and trivial development environment. However, for complicated applications like image data processing, theMCU‐based controller is unable to handle the complex data processing tasks and will dramatically degrade the performance of the embedded system.

The team at Aerotenna has designed a revolutionary, open source UAV platform - the Octagonal Pilot On Chip (OcPoC) - based on the Altera Cyclone V SoC to address these increased market needs.

The OcPoC flight control platform also supports Aerotenna’s microwave based altimeter, and a 360 degree collision avoidance radar.

 

Zongbo Wang, Aerotenna

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Smart Factory Case Study, Claudio Ambra, Exor

This case study presents how Exor developed the smart factory demo design; discussing the different connectivity technologies (OPC-UA, TSN, Ethernet protocols) used (including why they were chosen), the system design challenges (and how Exor overcame them), the benefits of the use of SoC based microSOMs and how the design can be extended to include different technologies and support other applications.

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Five Essential Hardware Security Controls for all Commercial SoC FPGA Projects

Today, theft of IP is placing the future of companies at risk. Every business needs to implement security in their products by default to prevent IP theft, product cloning and malware-injection attacks.  Governments and customers expect a base-line of security to be present in commercial products and systems.  Intel FPGA devices can easily deliver an essential base-line of hardware security in products at a negligible cost of ownership.  In this presentation we explore the key attack vectors that must be protected against in commercial projects, and the superior security solutions that can be easily employed in your new or current SoC FPGA projects. Some of these solutions can be retro-fitted to enhance existing products that are already deployed in the field

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Temporal vs. Spatial Compute

SoC FPGA devices provide a heterogeneous compute platform. In this study Netperf was used to assess the CPU load, performance and characteristics of a Linux based network processing application. The performance impact of offloading and tuning system parameters was assessed. In this presentation we compare these results with data measured on an FPGA fabric based solution. Portions of current compute workloads do not scale well with thread level parallelism (multi-core) and are bound by IRQ frequency or memory bandwidth limits. The approach of using the FPGA fabric within an SoC FPGA device as an additional compute core shows that, by trading off temporal vs. spatial computing, network processing in FPGA fabric can deliver high performance and systems that scale well.

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TSN: Deterministic Ethernet for Industrial, Automotive, and Railway

Time Sensitive Networking (TSN) represents a set of deterministic communication functions, standardized in IEEE 802.1 Ethernet.  TSN enables guaranteed, low-latency messaging between networked devices from different vendors. It also allows for the convergence of safety critical traffic with non-critical data and streaming traffic. These features are key building blocks for Industry 4.0 systems in manufacturing and for distributed control systems in automotive and railway. In these markets, Ethernet usage had previously been restricted due to its real-time performance limitations; TSN now provides ‘Guarantee of Service’ for Ethernet. With a long history and expertise in Deterministic Ethernet, TTtech will describe their Intel PSG based ‘Edge’ IP solutions for TSN networks. Implemented with the Cyclone V SoC device these solutions are ideally suited for Industrial and Automotive applications. TTTech will also describe extensions to TSN which deliver load-independent deterministic performance, better control in complex systems, and improved resilience.

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Smart Camera Designs, Interfaces, and Video Processing

Due to their ability to support accelerated algorithms and flexibility in connecting to different kinds of sensors and external interfaces, SoC FPGA devices make a good platform for the implementation of cameras in a wide range of different applications, e.g. machine vision, surveillance, smart cameras, TV cameras, industrial applications…. etc. We will describe some of the available options, future trends and existing evaluation kits for implementing:

  • Different sensor interfaces (LVDS, CMOS, MIPI,  etc.)
  • Video-Analytics in Software of with Hardware acceleration
  • Different outputs interfaces (Video over USB or GigE, Industrial Ethernet…)
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Highly Interactive Wireless Video Transfer Based on WiFi

There is an increasing demand for interactive industrial display applications with wireless connectivity. This requires low latency, real-time data transmission and high reliability. In general, these two requirements, low latency and high reliability, are contradictory. We will present a reliable, low-latency wireless video transfer system that uses the WiFi standard (IEEE 802.11) for data transfer. The sending device is Cyclone V SoC based and the display is a commercial tablet computer (iPad). In the Cyclone V FPGA, the video data is compressed and encoded using a low latency optimised Forward Error Correction (FEC) scheme. The ARM Cortex A9 processor of the SoC device controls the wireless module, the compression block in the FPGA as well as the data transfer over WiFi. We will discuss the challenges of low-latency compression, WiFi data transfer on a SoC and video decompression on a tablet computer in the GPU.

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