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O-RAN FPGA IP
Altera O-RAN IP delivers a flexible, standards-compliant fronthaul interface for 5G and LTE systems using the 7-2x functional split. Supporting both control and user planes per O-RAN-FH.CUS.0-v03.00, it simplifies DU-RU integration, accelerates development, and ensures interoperability in disaggregated, open RAN architectures.
By Altera
Optical Transport
We offer both OTN applications, such as Add/Drop Multiplexer (ADM), Muxponders, Transponders, Regenerators etc, for speeds from 1Gbps to 1.6 Tbps. Client support of Ethernet, Fibre Channel, OTN, SONET, and SDH. Line support of FlexO and OTU.Including all overhead processing, synchronization, software API / SDK
By Zeuxion ApS
QECIPHY - Free Open Source physical layer implementation
The physical layer of QECi (QECIPHY) allows data to be sent reliably between a control system and a QEC system. Our implementation of QECIPHY is available open source and can be easily integrated with any FPGA-based platform.
By Riverlane
Ultra Stable Micro Kelvin Temperature Measurement system
Ultra Stable Micro Kelvin Temperature Measurement Platform • Sub micro kelvin accuracy and stability • Compatible with cost efficient NTC and PT100 sensors • Ultra low noise ADC front end for exceptional signal integrity • Real time digital signal processing and temperature computation implemented as a high performance FPGA IP core
By Kendrion 3T
XAUI PHY FPGA IP
The XAUI PHY IFPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Altera FPGA to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module. You can implement the XAUI PHY in hard silicon in Intel's 65 nm and 40 nm FPGAs with serial transceivers faster than 3 Gbps. The PHY management functions are implemented in soft IP. In Intel 20 nm and beyond FPGA families, a XAUI PHY can be implemented in soft IP.
By Altera