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100G UDP IP Stack
Logic Fruit’s 100G UDP IP Stack – Optimized for high-speed 100G data transfer with minimal CPU dependency. Fully supports ARP and ICMP for reliable network connectivity and easy integration into SoC designs
By Logic Fruit Global Technologies Inc
10GBASE-R PHY FPGA IP
The 10GBASE-R PHY FPGA Intellectual Property (IP) core can be used with either Altera FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.
By Altera
ApSRAM Controller (will not be supported for FPGA devices, can be used during SoC Protyping in FPGA)
ApSRAM Controller is a low-latency, low-power IP scalable from 64Mb to 1Gb with multi-bank architecture for high throughput. Designed for AI/ML, edge, automotive, and IoT systems, it supports AXI interface and various silicon technologies. It simplifies SRAM replacement while ensuring compliance and interoperability.
By Mobiveil Inc.
ARINC 429 IP Core
Logic Fruit's ARINC 429 IP Core is a multichannel module with support for virtually any number of transmitters and Receivers. Both low speed (12.5 Kbps) and high speed (100 Kbps) data rates are supported for data transmission, along with other configurable data rates from 12.5 Kbps to 1 Mbps.
By Logic Fruit Global Technologies Inc
ARINC 818 IP CORE
ARINC 818 (ADVB) is a high data rate video bus based on the ANSI Fiber Channel Audio-Video (FC-AV) protocol standards. Emphasizing cost reduction as well as speeding up the link initialization. ARINC 818 is a unidirectional interface that was developed for avionics systems, such as connecting mission processors to cockpit displays like HUDS, MFDs, PFDs, or HMDs. Used widely in Boeing 787 and the KC46A tanker, Airbus A350 and A400M, the COMAC C-919, the C-17, F15, F18 and various military aircrafts.
By Logic Fruit Global Technologies Inc
DDR5/4 and LPDDR3/2 Controller (Silicon Proven IP for Altera Devices)
Mobiveil’s UMMC supports DDR5/4/3, LPDDR3/2, RLDRAM2/3, and 3DS memory interfaces for mobile, consumer, and networking applications. It provides high-bandwidth, low-power access with dynamic power management and high-frequency operation. The controller supports rapid debug and seamless SoC integration.
By Mobiveil Inc.
DISPLAY PORT IPs
Logic Fruit's Display Port Transmitter & Receiver IP Cores support multiple line rates up to 8.1 Gbps. The IP cores have been developed as per Display Port specifications DP2.0/eDP1.5.
By Logic Fruit Global Technologies Inc
FFT FPGA IP Cores
The Fast Fourier transform (FFT) FPGA intellectual property (IP) core is a high-performance, highly parameterizable FFT processor.
By Altera
HyperRAM Controller (Silicon Proven IP for Altera Devices)
The HyperRAM Controller supports Winbond’s HyperBus-based HyperRAM devices used in IoT, automotive, and industrial SoCs. Written in tech-agnostic Verilog RTL, it supports major simulation and synthesis tools. The controller ensures seamless memory integration with minimal resource usage.
By Mobiveil Inc.