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Agilex 7 F-Tile Ethernet Hard IP
The Agilex 7 FPGA F-Tile IP core implements Ethernet at data rates of 10 Gbps, 25 Gbps, 40 Gbps, 50 Gbps, 100 Gbps, 200 Gbps and 400 Gbps. The user can choose a media access control (MAC) and a physical coding sublayer (PCS) variation, a PCS-only variation, a Flexible Ethernet (FlexE) variation, or an Optical Transport Network (OTN) variation.
By Altera
Arria® 10 and Cyclone® 10 PCIe Hard IP
Configurable PCIe 3.0/2.0 hard IP on Arria® 10 & Cyclone® 10 GX FPGAs with Root Port/Endpoint, Avalon-ST, Avalon-MM, and SR-IOV and DMA options.
By Altera
Backplane Ethernet 10GBASE-KR PHY FPGA IP
The Backplane Ethernet 10GBASE-KR PHY Altera FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instantiate the hard standard physical coding sublayer (PCS), the higher performance hard 10G PCS, and the hard physical medium attachment (PMA) for a single Backplane Ethernet channel.
By Altera
CIC FPGA IP Core
The CIC FPGA IP core offers computationally efficient cores for extracting baseband signals.
By Altera
Compute Express Link (CXL) IP
CXL IP is designed to provide the added memory bandwidth and capacity, and acceleration needed for a wide range of data-intensive workloads.
By Altera
CPRI FPGA IP
Altera CPRI FPGA IP delivers a high-performance, standards-compliant implementation of the CPRI Specification V7.0, enabling reliable, high-speed communication between Radio Equipment Controllers (RECs) and Remote Radio Equipment (REs). Fully configurable as either REC or RE, the IP simplifies integration in remote radio network applications and accelerates deployment of robust, low-latency fronthaul links.
By Altera
DDR5 and DDR4, LPDDR5 and LPDDR4 External Memory Interfaces FPGA IP
DDR4 and DDR5 offer higher bandwidth and improved performance over previous generations, with DDR5 providing further enhancements in speed and power efficiency. LPDDR4 and LPDDR5 are optimized for low power consumption, making them ideal for embedded applications, with LPDDR5 offering even faster data rates and improved energy management. When integrated with Altera FPGAs these memory technologies enable faster data processing and more efficient power usage for a wide range of applications including networking, cloud and edge.
By Altera
eCPRI FPGA IP
Altera eCPRI FPGA IP implements the eCPRI 2.0 specification, providing a high-performance front-haul interface for next-generation radio base stations. It enables seamless, low-latency connectivity between eCPRI Radio Equipment Control (eREC) and Radio Equipment (eRE) over front-haul transport networks, accelerating deployment of scalable, flexible 5G infrastructure.
By Altera
F-Tile PCIe Hard IP
F-Tile is an FPGA companion tile that supports PCI Express* configurations up to PCIe 4.0 x16 in Endpoint (EP), Root Port (RP) and Transaction Layer (TL) Bypass modes. PCIe 3.0 and 4.0 configurations are natively supported.
By Altera