from Altera

 

The Altera® Arria® II GX FPGA Development Kit delivers a complete system-level design environment that includes both the hardware and software needed to immediately begin developing FPGA designs. With this PCI-SIG®-compliant board and a one-year license for Quartus® Prime design software, you can:

  • Develop and test PCI Express® (PCIe®)1.0 (up to x8 lane) designs
  • Develop and test memory subsystems consisting of DDR2 and DDR3 memory
  • Develop and test designs based on other protocol interfaces supported by the Arria II GX FPGA, such as Gbps Ethernet (GbE), serial digital interface (SDI), Common Public Radio Interface (CPRI), OBSAI, SAS/SATA, and Serial RapidIO® (SRIO). Many of these are supported by taking advantage of this board's modular capability through the high-speed mezzanine card (HSMC) connectors and over 20 different HSMC connectors available through Altera partners.

Arria II GX FPGAs also support other protocols.

Ordering Information

Table 1. Arria II GX FPGA Development Kit Ordering Code and Pricing Information

Ordering Code Price Ordering Information
DK-DEV-2AGX125N

$1,495

Buy online via Altera´s eStore or contact your local Altera distributor to place your order.
Notes:

Buyer represents that it is a product developer, software developer or system integrator and acknowledges that this product is an evaluation kit that is not FCC authorized, is made available solely for evaluation and software development, and may not be resold.

Other HSMC-compatible daughtercards, adapters, or cables are also available.

HSMC Interface

Altera developed the specification for the HSMC, which is based on the Samtec mechanical connector, to define and standardize the interface between optional daughtercards and host boards. This specification outlines both the electrical and mechanical properties of the interface between daughtercard and host. You can also create your own HSMC interface-compatible daughtercards.

 

Development Kit Contents

The Arria II GX FPGA Development Kit is restriction of hazardeous substances (RoHS) compliant and features the following:

  • Arria II GX EP2AGX125EF35 FPGA in the 1152-pin fine-pitch ball-grid array (BGA) package
    • 124,100 logic elements (LEs)
    • 49,640 adaptive logic modules (ALMs)
    • 8,121 kilobytes (KB) on-chip memory
    • 12 high-speed transceivers
    • Six phase-locked loops (PLLs)
    • 576 18x18 multipliers
    • 0.9 V core power
  • MAX® II EPM2210F256 CPLD in the 256-pin fine-pitch BGA package
    • 2.5 V core power
  • On-board ports
    • One HSMC expansion port
    • One GbE port
  • On-board memory
    • 128 MB 16-bit DDR3 SDRAM device
    • 1 GB 64-bit DDR2 SDRAM 64 MB flash memory
  • FPGA configuration circuitry
    • MAX II CPLD and flash fast passive parallel configuration
    • On-board USB-Blaster™ circuitry using the Quartus Programmer
  • On-board clocking circuitry
    • Four on-board oscillators
      • 100 MHz
      • Programmable oscillator, default frequency 125 MHz
      • Programmable oscillator, default frequency 100 MHz
      • 155.52 MHz
    • SMA connectors for external LVPECL clock input
    • SMA connector for clock output
  • General user I/O pins
    • Displays
      • Four user LEDs
      • Two-line character LCD display
      • One configuration-done LED
      • One HSMC interface transmit/receive LED (TX / RX)
      • Three PCIe LEDs
      • Five Ethernet LEDs
  • Push-buttons
    • One user reset (CPU reset)
    • One MAX II CPLD reset
    • One load image (program FPGA from flash)
    • One image select (select image to load from flash)
    • Two general user push-buttons
  • Dual in-line package (DIP) switches
    • Four user DIP switches
    • Eight MAX II device control DIP switches
  • Power supply
    • 14 V to 20 V DC input
    • PCIe edge connector power
    • On-board power measurement circuitry
  • Mechanical
    • PCIe full-length standard-height (8.48” x 4.376”)
    • PCIe chassis or bench-top operation
  • Arria II GX FPGA Development Kit CD-ROM
    • Design examples
      • Board Update Portal, featuring the Nios® II processor web server and remote system update
      • Board Test System
    • Complete documentation (see Table 2)
  • Altera's complete Quartus Prime Design Suite (download from Altera Download Center)
    • Quartus Prime design software, includes support for Arria II GX FPGAs
      • Includes one-year license
    • Nios II Embedded Design Suite
    • MegaCore® IP Library includes PCIe, Triple-Speed Ethernet, SDI, and DDR3 SDRAM High-Performance Controller intellectual property (IP) cores
      • IP evaluation available through OpenCore Plus
  • Power adaptor and cables

Figure 1. Arria II GX FPGA Development Board

Available Documentation

Table 2. Documents Available for the Arria II GX FPGA Development Kit

Document Description Format Language Quartus Software Version
Arria II GX FPGA Development Kit User Guide (PDF)

Information about setting up the Arria II GX FPGA development board and using the included software

PDF

English n/a
Arria II GX FPGA Development Board Reference Manual (PDF)

Detailed information about board components and interfaces

PDF English n/a
Kit Installation (via FTP)

(Updated) Full installation of all files including reference manual, user guide, quick start guide, demos and tutorials, bill of material (BOM), layout, PCB, schematics, Board Update Portal example file, Board Test System example file, and others

Restore fast configuration feature from BTS GUI menu

PDF and Microsoft Excel

English 12.1.0
Kit Installation (via FTP)

(Archive) Full installation of all files including reference manual, user guide, quick start guide, demos and tutorials, bill of material (BOM), layout, PCB, schematics, Board Update Portal example file, Board Test System example file, and others

12.0.0
Kit Installation (via FTP)

(Archive) Full installation of all files including reference manual, user guide, quick start guide, demos and tutorials, BOM, layout, PCB, schematics, Board Update Portal example file, Board Test System example file, and others

Board Update Portal is upgraded to Qsys

11.1.0
 


Reference Designs and Design Examples

Table 3 provides a list of Arria II GX designs, not delivered with the kit, but available for download.

Table 3. Designs for the Arria II GX FPGA Development Kit

Design Name Other Software Requirements (1) Other Hardware Requirements Availability
PCI Express high-performance reference design
  • PCI Express x4-to-x1 lane converter
  • Two computers, one with a PCIe x8/x4/x1 slot
Now
PCI Express to External Memory reference design
  • Two computers, one with a PCIe x8/x4/x1 slot

Now

Note:

  1. Quartus Prime design software and the MegaCore IP Library are standard software requirements for all kits.