Arria V GX FPGA Development Kit

from Intel® (Formerly Altera)

The Altera® Arria® V GX FPGA Development Kit provides a complete design environment that includes all the hardware and software that you need to develop full FPGA designs and test them within a system environment. The development kit includes the following features:

  • Two FPGAs for system-level design
    • Arria V GX FPGA: 360K logic elements (LEs), F1517 package, 24 6G tranceivers, and C5 speed grade
  • Three I/O expansion slots: two high-speed mezzanine cards (HSMCs) and one FPGA mezzanine card (FMC)
  • 2 GB of DDR3 SDRAM memory, 4.5 MB of QDR II+ memory, and 1 Gb of flash memory
  • SFP+ connections
  • SMAs 
  • Ability to measure individual power rails on each chip

Ordering Information

Table 1. Altera's Arria V GX FPGA Development Kit Ordering Information

Ordering Code Price Ordering Information

DK-DEV-5AGXB3N/ES

$3,995


Buy Now

The Arria V GX FPGA Development Kit features a 5AGXB3 Engineering Sample (ES) device and a one-year license for the Quartus® Prime design software.

Contact your local Intel® FPGA distributor to place your order.

Note:

  1. Buyer represents that it is a product developer, software developer or system integrator and acknowledges that this product is an evaluation kit that is not FCC authorized, is made available solely for evaluation and software development, and may not be resold.
  2. You can purchase optional HSMC and FMC connector interface-compatible daughter cards, adapters, or cables to use with your development kit.

Development Kit Contents

The Arria V GX FPGA Development Kit features the following:

  • Arria V GX FPGA development board (see Figure 1)
  • Unit 1: Arria V GX FPGA: 5AGXFB3H4F40C5NES
    • Memory
      • 1,152-MB x72 DDR3 SDRAM
      • 4.5-MB (1 Mb x 36) QDR II+ SRAM
      • 1-Gb sync flash (x16)
    • Communication ports
      • PCI Express® (PCIe®) x8 edge connector
      • HSMC Port A (four transceiver channels)
      • USB 2.0
      • Gbps Ethernet
      • Chip-to-chip bridge with 29 LVDS inputs and 29 LVDS outputs, and x8 transceivers
      • One SFP+ channel
      • Bullseye connector (x1 channel)
      • SMA connectors (x1 channel)
    • Configuration
      • JTAG
      • Fast passive parallel (FPP) parallel flash loader (PFL)
    • Buttons, switches, LEDs, and displays
      • One reset configuration push button
      • One CPU reset push button
      • Three user push buttons
      • Two configuration push buttons
      • Eight dual in-line package (DIP) switches
      • 16 user LEDs (eight bi-color diodes)
      • 16x2 character LCD
  • Unit 2: Arria V GX FPGA: 5AGXFB3H4F40C5NES
    • Memory
      • x64 DDR3 SDRAM soft controller (or x32 hard intellectual property (IP) controller)
    • Communication ports
      • HSMC Port B (four transceiver channels)
      • FMC Port (four transceiver channels)
      • Chip-to-chip bridge with 29 LVDS inputs and 29 LVDS outputs, and x8 transceivers
      • One serial digital interface (SDI) channel
      • Bullseye connector (one transceiver channel)
      • SMA connector (one transceiver channel)
    • Configuration
      • JTAG
      • FPP PFL
    • Buttons, switches, LEDs, and displays
      • One CPU reset push button
      • Three user push buttons
      • Eight DIP switches
      • 16 user LEDs (eight bi-color diodes)
  • Miscellaneous
    • EPM2210GF324 system controller
    • EPM570GM100 on-board USB-Blaster II download cable
  • Clocking
    • 50-MHz oscillator
    • 100-MHz and 125-MHz programmable oscillators
    • SMA input (LVPECL)
  • Power
    • Laptop DC input
    • PCIe edge connector
  • System monitoring
    • Power (voltage, current, and wattage)—per unit per rail
    • Temperature (per FPGA die, local board)
  • Loopback and debug HSMC cards
  • Power adapter and cables
  • Arria V GX FPGA Development Kit software content
    • Complete documentation
      • User guide
      • Reference manual
      • Board schematics and layout design files
    • GUI-based Board Test System
      • Includes complete Quartus software projects with open source register transfer level (RTL)
    • Board Update Portal
      • Includes complete Quartus software projects with open source RTL
    • Quartus Prime design software, Development Kit Edition (DKE)
      • License to use full version of Quartus Prime design software for one year
  • Go to Top

Figure 1. Arria V GX FPGA Development Board with an 5AGXB3ES FPGA

Figure 2. Arria V GX FPGA Development Board Block Diagram

Available Documentation

Table 2. Documentation for Arria V GX FPGA Development Kit

Kit Name

(Ordering Code)

Document Description Version

Arria V GX FPGA Development Kit

(DK-5AGXB3N/ES)

Arria V GX FPGA Development Board Reference Manual (PDF) Detailed information about board components and interfaces 12.0
  Arria V GX FPGA Development Kit User Guide (PDF) Information about setting up the Arria V GX FPGA development board and using the included software 12.0
  Kit installation (via FTP) Full installation of all files including reference manual, user guide, quick-start guide, BOM, layout, PCB, schematics, Board Update Portal example file, Board Test System example file, etc. 12.0