Altera CPLDs

Since 1993 Altera's MAX® CPLD series has provided the lowest power, lowest cost CPLDs.

Since 1993 Altera's MAX® CPLD series has provided the low power, low cost CPLDs. The introduction of the new MAX 10 FPGAs present a leap forward in integration and FPGA capabilities for a non-volatile programmable logic device.

Table 1. MAX Series

  Mature CPLD Families MAX II
Year of Introduction 1995 - 2002 2004 2007 2010 2014
Process Technology 0.50-0.30 µm 180 nm 180 nm 180 nm 55 nm
Key Features 5.0 V I/Os High I/O count Low static power Low cost and power Non-volatile integration
Low-Cost Devices Description/Unique Features

  • Single-chip, dual-configuration non-volatile FPGA
  • Optimal system component integration for half the PCB space of traditional volatile FPGAs
  • Broad range of intellectual property (IP) including analog-to-digital converters (ADCs), digital signal processing (DSP), and the Nios® II processor

  • Robust features at up to 50 percent lower total power vs. competitive CPLDs
  • Lower total system cost through architecture that integrates previously external functions
  • Instant-on, single-chip CPLD built on non-volatile architecture

  • Instant-on, non-volatile, single-chip CPLD solution
  • 1/10th the power of MAX® CPLDs, with low cost, low power, and high density
  • On-board user flash memory. 1.8 V, 2.5 V, and 3.3 V supply voltages