MAX II Low-Cost Architecture

Based on a groundbreaking new CPLD architecture, MAX® II devices redefine the value proposition for CPLDs. Traditionally, CPLDs have been implemented with macrocell-based logic array blocks (LABs) and deterministic global routing matrices. Macrocell-based architectures are not efficiently scalable to densities greater than 512 macrocells due to the exponential increase in routing area as logic densities increase (see Figure 1).

At higher densities, look-up table (LUT)-based LABs and row-and-column routing are more die-size and cost efficient. Because MAX II CPLDs are based on an LUT architecture, they deliver a major cost reduction, which, combined with instant-on, non-volatility and re-programmability, make the MAX II family the lowest-cost CPLDs ever.

Figure 1. Low-Cost MAX II CPLD Architecture Delivers Smaller Die Size


  1. Routing increases exponentially with number of LABs, resulting in a routing-based dominated die.
  2. Routing increases linearly with number of LABs, resulting in efficient die size.

Designed for Low Cost

MAX II CPLDs are built using a low-cost design methodology that start with a selection of popular, low-cost packages. A minimum die size is achieved by using a pad-limited, staggered I/O pad arrangement, resulting in the lowest-cost-per-I/O pin. The device is then populated with the maximum number of logic elements (LEs) that fit inside of the I/O ring. This LUT-based architecture delivers the maximum possible logic capability in the smallest I/O-constrained space.

MAX II Architecture

The groundbreaking MAX II CPLD architecture includes an array of LUT-based LABs, a bank of non-volatile flash memory, and JTAG control circuitry (see Figure 2). The MultiTrack interconnect is designed to maximize performance and minimize power by using the most efficient, direct connection from input to logic to output. More details about the MAX II architecture are available in the MAX II Device Family Data Sheet (PDF).

Figure 2. MAX II CPLD Device Floorplan

Designed in Concert with Quartus II Software

To simplify the design optimization process, the MAX II CPLD architecture and Quartus® II software fitting algorithms were refined in concert to optimize tPD, tCO, tSU, and fMAX performance with pins locked down. As design functionality changes, the Quartus II software enhances the ability to meet or exceed performance requirements using locked pin assignments and a push-button compilation flow. All MAX II CPLDs are supported by the no-cost Quartus II Web Edition software.

Voltage Flexibility

The MAX II CPLD architecture supports a MultiVolt core, which allows these CPLDs to operate with a 1.8-V, 2.5-V, or 3.3-V supply voltage. There are three product family options available depending on supply voltage (see Table 1 and Figure 3). This feature allows you to minimize the number of power rails and simplify the board-level design.

Table 1. Supply Voltage Options

Preferred Supply Voltage

MAX II Ordering Code Suffix

3.3 V


2.5 V


1.8 V

G or Z


Figure 3. MultiVolt Core Operation


  1. VCCINT = 1.8-V bypasses the regulator.

MAX II CPLDs also support Altera’s MultiVolt I/O interface feature, which allows seamless interface to other devices at 1.5-, 1.8-, 2.5-, or 3.3-V logic levels (see Figure 4). The EPM240 and EPM570 devices have two I/O banks, and the EPM1270 and EPM2210 devices have four I/O banks. Each bank can be supplied with an independent VCCIO.

Figure 4. MultiVolt I/O Capability