Real-Time ISP with MAX II CPLDs

MAX® II CPLDs feature real-time in-system programmability (ISP). Real-time ISP reduces maintenance costs by allowing you to program a device while the device is in operation. This feature enables quick in-field product updates without requiring the system to be turned off to initiate reconfiguration.

The separation of the flash configuration block and the programmable logic block in MAX II CPLDs makes real-time ISP possible. The updated design can be immediately loaded into the device or can be instructed to wait for the next power cycle. With real-time ISP, MAX II CPLDs can quickly be updated without expensive system downtimes or dispatching personnel to customer locations.

Additionally, real-time ISP allows multiple designs to run on a single device and updates to occur independently without affecting each other. In the remote update application shown in Figure 1, the FPGA configuration design can be updated with only momentary disruption to the microcontroller I/O expansion.

Figure 1. Typical Remote Field Update Application (FPGA Configuration)

Notes:

  1. POR: Power on reset
  2. JTAG: Joint Test Action Group

How to Use Real-Time ISP

The first step in using real-time ISP is to send the programming bitstream via a fixed or remote link (such as a telephone modem or an Ethernet connection) to the application's system (see Figure 2). Then the remote update system sends the data through the JTAG port to the configuration flash memory, where it is stored.

During this download, the user flash memory, programmable logic, and I/O pins remain operational, enabling uninterrupted operation. Uninterrupted I/O pin operation means all pins stay in a known state, and no glitches are introduced during the update. Given that the system remains operational, the download of the new programming bitstream to the configuration memory can happen at any time.

Figure 2. Download of Programming Bitstream

The new downloaded bitstream can immediately update the programmable logic (see Figure 3), during which the I/O pins enter tri-state while the download to the programmable logic is completed. Alternatively, the new programming bitstream can remain in the configuration flash memory until the next power cycle, which can be determined according to convenience (when system use is low). The user flash memory can also be updated at this point to store new system management data (the date of the programming change).

Figure 3. Logic Configuration

Alternative Applications

There are a number of other applications that can benefit from the real-time ISP feature. A CPLD used to run a secure cipher can be updated with a new code while in operation, taking effect on the next power cycle. The higher MAX II CPLD densities can also enable test and diagnostic programs to be run and updated while the final production design is operational.