Q. How does the MAX II device conserve battery life for portable applications?
A. A MAX II low-power CPLD can be completely powered-down because of its superior hot-socket, power-sequence flexibility, and single power supply simplicity. More information on the power-down capability is available on the MAX II Low-Power page.
Q. How does the MAX II CPLD family's performance compare with prior generation MAX CPLDs?
A. The MAX II family’s performance is on average twice as fast as the previous-generation MAX CPLDs.
Q. How do the speed grades relate to the tpd specification?
A. The speed grades describe the relative speed of each device. The -3 is the fastest, the -4 is the medium, and the -5 is the slowest speed grade. The "fastest tpd1" specification in the MAX II Device Handbook correlates to the fastest commercial speed grade, which is a corner-to-corner delay path through the device.
Q. MAX II CPLDs and Stratix® II FPGAs have the same speed grades. Are the performance specifications the same?
A. For both the MAX II and Stratix II families, the -3 speed grade is the fastest, -4 is the medium, and -5 is the slowest. Even though the speed grade nomenclature is the same, the performance specifications are not.
Q. Are the MAX II devices pin-compatible with prior generation MAX CPLDs?
A. No. MAX II CPLDs are based on a completely new architecture and are, therefore, not pin-compatible with Altera’s MAX 7000 or MAX 3000 device families.
Q. Why are fewer user I/O pins available when you migrate to a higher-density device in the same package?
A. Each MAX II CPLD family member is optimized for the highest possible number of I/O pins in the lowest density device for a given package. Because of higher LE counts, high-density members require a greater number of power and ground pins to operate correctly. For any given package, therefore, the number of available user I/O pins must be reduced when a denser device is used.
Q. What is the power-on time for this instant-on family?
A. The smallest MAX II device (EPM240) powers-on in less than 200 microseconds, from the time the supply voltage meets the minimum VCC. The EPM570 and EPM2210 devices power-up in less than 300 microseconds. The largest MAX II device (EPM2210) powers-on in less than 450 microseconds, from the time the supply voltage meets the minimum VCC.
Q. What is the difference between the user flash memory and the configuration flash memory?
A. The user flash memory allows you to integrate discrete serial or parallel non-volatile storage onto MAX II CPLDs. The configuration flash memory, which is not user accessible, is employed internally to store the programmed design information that is subsequently loaded into the programmable logic.
Q. Can MAX II devices be in-system programmed?
A. Yes. The MAX II CPLDs support in-system programmability through the JTAG ports using .pof, JamTM STAPL, .svf, or IEEE 1532 files.
Q. Are there any phase-locked loops (PLLs) available in MAX II CPLDs?
A. No. There are no PLLs available in MAX II CPLDs. The die size, power requirements, and clock pins required for PLLs would have increased device cost above desired levels.
Q. Which single-ended I/O electrical standards does the MAX II CPLD family support?
A. MAX II CPLDs support a variety of single-ended I/O standards, including LVTTL, LVCMOS, and PCI. MAX II CPLDs also support a programmable slew rate and drive strength control for certain I/O standards.
Q. Does the MAX II CPLD family support hot socketing?
A. Yes. The
VCCINT power pins can be powered-up in any order. In addition, signals can be driven into the MAX II devices before and during power-up (and power-down) without damaging the device, because device I/O pins do not source or sink more than 300 µA of DC current during these operations.
Q. Which I/O voltages does the MAX II CPLD family support?
A. The MAX II CPLDs have up to four I/O banks that seamlessly interface to other devices at 3.3-, 2.5-, 1.8-, and 1.5-V logic levels.
Q. Are MAX II CPLDs 5.0-V tolerant?
A. The two larger MAX II CPLDs are 5.0-V tolerant when used with an external series resistor and the on-chip PCI clamping diode. The two smaller devices are not 5.0-V tolerant.
Q. Do MAX II CPLDs support PCI?
A. The two largest MAX II CPLDs support 66-MHz, 32-bit PCI.
Software and Intellectual Property
Q. Which versions of the Quartus® II design software support MAX II CPLDs?
A. All MAX II CPLDs are supported by the Quartus II Web Edition software version 4.0 or higher, which you can download for free. The full version of the Quartus II design software version 4.0 or higher, available through Altera’s subscription program, also supports all MAX II devices. Programming file generation for the MAX II CPLDs will also be supported in a subsequent software release.
Q. Does the MAX+PLUS® II design software support MAX II CPLDs?
A. No. MAX II CPLDs are supported in the Quartus II design software, versions 4.0 or higher.
Q. Which third-party tools support MAX II CPLDs?
A. Synthesis and simulation tools from leading EDA vendors Mentor Graphics® (Precision 2003C) and Synplicity (Synplify 7.5.1) support the MAX II CPLD family to ensure the highest quality design implementation.
Q. Which intellectual property (IP) cores are available for MAX II CPLDs?
A. Altera offers a PCI core for the MAX II CPLDs. Support will also be provided for a select number of common interfacing cores, including I2 C, SPI, and UARTs.
Q. What MAX II development kits are available?
A. Altera currently recommends two low-cost development kits shown in the table below.