||Manufactured using a mature, long-life cycle, low-cost 0.18-µm fab process combined with the latest low-cost packaging technologies.
||Up to 50% lower total power compared to equivalent density competitive CPLDs, generating less heat and saving battery power.
||Replaces an external discrete timing devices for use as a simple clocking source, saving BOM costs.
|Fast power-on and reset
||Power on and reset quickly (500 µs or less), ideal for power management, power sequencing, and monitoring of other devices on the PCB.
|Realtime in-system programmability (ISP)
||Allow you to update a second configuration image while the CPLD is in operation.
||I/Os are hot-socket compliant and support LVTTL, LVCMOS, PCITM, and LVDS output interface standards, along with other bus-friendly options (e.g. output enable per pin, Schmitt triggers, slew rate control, and others).
||All packages are available in restriction of hazardeous substances (RoHS)-compliant variants, meeting the "low-halogen" requirements per JEDEC document JED 709 (draft). Selected packages are available in leaded variants.
|Parallel Flash Loader
||The on-chip JTAG block can configure external non-JTAG-compliant devices, such as discrete flash memory devices, using the Parallel Flash Loader IP Megafunction.