When you download Altera Complete Design Suite (ACDS) v14.0 you will get the latest enhancements and new features for Altera’s embedded products which include SoCs and Nios® II processor.

Nios II Gen2 Processor Support

ACDS v14.0 introduces software (binary) compatible new (preview) implementations of the Nios II processor cores. The Nios II Embedded Design Suite (EDS) contains minor changes to support the additional features of the new Nios II Gen2 processor cores so it is recommended that users re-generate the board support package (BSP) and rebuild the application when using the Gen2 cores. The Nios II Gen2 processor core changes compared to the previous Nios II core versions include:

  • Improved Qsys GUI wizard
  • Removal of Nios II /s core option (note: the same configuration as the /s can now be achieved by configuring the Nios II Gen2 /f core appropriately)
  • Nios II Gen2 /e core now has the option for 32 bit address range support
  • Nios II Gen2 /f core updates:
    • Optional 32 bit address range
    • Optional peripheral (uncached) memory region (configurable size, for use when 32 bit address range is selected)
    • When an uncached write is made, the cache is no longer updated, hence software developers should take this into account in their code
    • Optional static branch prediction
    • Optional error correction code (ECC) on data cache and tightly-coupled memories (instruction and data)
    • Higher performance multiply (32 bit mult. 5 cycles -> 1 cycle)
    • On average, higher-performance divide that is more deterministic
    • 64 bit multiply supported on all devices (not just those with digital signal processing (DSP) blocks)
    • Improved low-cost shifter implementation (1 bit/cycle -> 4 bits/cycle)
    • Instruction cache is now optional even when JTAG debug present
    • More flexible configuration of JTAG Debug options (i.e. numbers of hardware breakpoints, triggers)
    • Off-chip trace now has an Avalon® streaming (Avalon-ST) interface (requires addition of intellectual property (IP) to bridge Avalon-ST -> trace probe connection, available from trace tool vendors)

MAX® 10 and Arria® 10 FPGAs are only supported by Nios II Gen2 processors. The previous generation of Nios II processors are not supported with MAX 10 or Arria 10 FPGAs.

Nios II EDS 14.0 Updates and Fixes

The v14.0 Nios II Software Build Tools (SBT) only runs on 64 bit hosts systems, 32 bit hosts are no longer supported (gdb-server and the flash programmer remain 32 bit).
Run time stack checking has now been fixed and the compiler now supports long jumps (>256Mb) correctly. The address span expander and IRQ bridge IP are now fully supported.

SoC Design Examples

New SoC hardware designs are available:

  • ARM® + Nios II Hardware Reference Design (AMP Proof of Concept)
  • Cyclone® V or Arria V FPGA PCI Express® (PCIe®) RP design example
  • Cyclone V SoC TSE-mSGDMA design example
  • Cyclone V or Arria V SoC GHRD

SoC EDS v14.0

The SoC EDS v14.0 contains the following additions/improvements:

  • 64 bit support for host tools
    • 64 bit versions of ARM® Development Studio 5 (DS-5TM) and Cygwin, 32 bit hosts are no longer supported
    • Baremetal and Linux ARM gcc toolchains remain at 32 bit
  • Preloader support for HPS clock configuration
  • SD card updater tool for preloader and uboot
  • Updated ARM baremetal gcc toolchain with library support for hard floating point
    • arm-none-eabi-gcc is now arm-altera-eabi-gcc
  • DS-5 has improved support for baremetal development including gcc support
  • Out-of-box improvements
    • DS-5 upgrade to 5.17
    • Cygwin upgrade to 1.7.27
    • Linux Kernel support upgraded to kernel version 3.13
    • DS-5 toolchain extension support
    • DS-5 install directory location is now flexible [windows only]
    • Installer now installs uart2usb and USB-BlasterTM II drivers
    • BSP Editor can be launched outside of embedded command shell
    • Sopc2dts improvements to simplify boardinfo.xml files

Arria 10 and Arria10 SoC devices are supported in a separate ACDS release.

Updates for Nios II Processor in Quartus II v13.1 Software Tool

  • GCC upgrade to v4.7.3
    The v13.1 Nios® II EDS/SBT supports v4.7.3 version of GCC for smaller code size and compatibility with the latest versions of currently available from rocketboards.org.
  • Enhanced floating-point custom instruction support
    Get the option to select a new floating-point custom instruction set component in the Qsys Tool. The component has one combinatorial custom instruction and one multi-cycle custom instruction. The combinatorial custom instruction implements comparison, minimum, maximum, negate, and absolute operations. The multicycle custom instruction implements add, subtract, multiply, divide, square root, and conversion operations. These are binary compatible with the previous custom instructions, but offer superior performance (fewer cycles operation).
  • ECC support
    The optional ECC in the Nios II configuration wizard enables ECC protection on the RAMs inside the processor core and the instruction cache (data cache with ECC enabled is currently not supported). Single-bit soft errors are corrected and dual-bit soft errors cause either an instruction cache flush or processor exception. Only available on the Nios II /f core without data cache.
  • Register transfer level (RTL) Nios II processor trace simulation support
    This feature enables recording and time-stamping of Nios II processor instruction execution during RTL simulation in ModelSim® Altera software edition of events such as instruction execution and address, data address and value, interrupts, and control register changes.The timestamp allows the developer to align hardware simulation data with software execution.

Breakthrough Advantages with Generation 10 FPGAs and SoCs

Altera introduced its Generation 10 FPGAs and SoCs, offering system developers breakthrough levels of performance and power efficiencies. Generation 10 devices are optimized based on process technology and architecture to deliver the industry's highest performance and highest levels of system integration at the lowest power. Initial Generation 10 families include Arria 10 and Stratix® 10 FPGAs and SoCs with embedded processors. Generation 10 devices leverage the most advanced process technologies in the industry, including Intel's 14 nm Tri-Gate process and TSMC's 20 nm process.