Frequently Asked Questions—Embedded Soft Processors

Q. What soft processors are available for Intel® FPGAs?
A. There are several soft processor choices:

Nios II Embedded Processor

Q. What is the Nios II embedded processor?
A. The Nios II embedded soft processor is a general-purpose, 32 bit RISC CPU optimized for programmable logic. Three distinct processor cores provide maximum design flexibility, balancing system performance needs and logic element (LE) usage:

  • Nios II/f (fast)—highest performance, moderate FPGA utilization
  • Nios II/s (standard)—high performance, low FPGA utilization
  • Nios II/e (economy)—modest performance, lowest FPGA utilization

Nios II processor architecture:

  • 32 bit instruction set architecture
  • 32 bit data and address paths
  • 32 general-purpose registers
  • 32 external interrupt sources
  • Configurable instruction cache (/f and /s cores only)
  • Configurable data cache (/f core only)
  • Common interface for up to 256 custom instructions
  • Up to four tightly coupled memories

Learn more about Nios II processor cores.

Q. Who is using Nios II processors today?
A. With over 20,000 kits shipped and the world’s top 20 OEMs already using the Nios II processor, the Nios architecture is the most popular configurable soft processor available today.

Q. Which Intel FPGA series or ASICs support the Nios II processors?
A. Nios II processors are fully supported by the Stratix®, Arria® GX, and Cyclone® SoC and FPGAs.

Q. How much performance does the Nios II processor deliver, and how much logic does it consume?
A. The performance and logic utilization of the Nios II processor depend heavily on the processor configuration and device family used. The Nios II Performance Benchmarks (PDF) data sheet provides benchmarks for various configurations and FPGA usage.

Q. What hardware development tools are provided for designing with the Nios II processor?
A. Intel provides a complete set of design tools for the Nios II processor:

  • System integration tools— The Platform Designer (formerly Qsys) lets you select the system components (that is, processor, peripherals, memories, and so on) from a comprehensive list of IP cores using a GUI. The Platform Designer (formerly Qsys) generates the system interconnect logic automatically, outputs HDL files that define all components of the system and a top-level HDL design file that connects all the components together, and creates a system testbench. The Platform Designer (formerly Qsys) also allows you to create your own reusable custom components and add them to the pool of available IP cores. Learn more about the Platform Designer (formerly Qsys).
  • FPGA design software—The Intel Quartus® Prime design software provides a complete, multiplatform design environment for all phases of FPGA and CPLD design. Learn more about FPGA design flow.
  • Embedded software development tools—The Nios II processor Embedded Design Suite (EDS) provides a complete set of design and debugging tools for the embedded software developer. Learn more about embedded software design tools.

All hardware and software components needed to design a Nios II processor-based system (Nios II processor EDS, IP, Platform Designer (formerly Qsys), and Intel Quartus Prime design software) are available for free download from the Intel website and are included in Intel's development kits. Download Nios II design tools.

Q. Can I try the Nios II embedded processor (and toolchain) before I buy it?
A. Yes. You can download and design with the latest (fully functional) release of the Nios II embedded processor for free from the Intel website. However, before shipping a product containing a Nios II processor-based system you must purchase a license.

Q. What are custom instructions and how do they work?
A. Custom instructions are user-developed hardware blocks that extend the Nios II processor instruction set to accelerate software algorithms. Up to 256 custom instructions can be added per Nios II processor core. The Nios II processor software development tools automatically generate macros that can be called from within a C application and operate much like a C subroutine call, with zero overhead. Similar to native Nios II processor instructions, custom instruction logic can take values from up to two source registers and (optionally) write back a result to a destination register. A library of general-purpose and floating-point custom instructions are provided with the Nios II processor IP. Learn more about custom instructions.

Download Nios II Custom Instruction User Guide (PDF).

Q. What are tightly coupled memories and how do they help?
A. A tightly-coupled memory is fast on-chip memory that bypasses the processor cache and has guaranteed low latency and provides the best memory access performance.

Download Using Tightly Coupled Memory with the Nios II Processor Tutorial (PDF).

Q. What is the system interconnect fabric?
A. The system interconnect fabric is a true, nonblocking interconnect automatically created by the Platform Designer (formerly Qsys) that supports multiple simultaneous master-slave transactions and therefore delivers dramatic improvements in overall system performance compared to traditional shared media bus structures. The system interconnect fabric requires minimal FPGA resources and supports the following:

  • Simultaneous multiple master operation
  • Up to 4 gigabytes (GB) of address space
  • Synchronous interface
  • Built-in address decoding
  • Read and write transfers with latency
  • Streaming transactions
  • Dynamically sized peripheral interface
  • Multiple clock domains
  • Pipelined operation

Learn more about the system interconnect fabric.

Download Avalon® Interface Specifications (PDF).

Q. What do I need to know to create my own peripherals to use with the Nios II processor?
A. The Platform Designer (formerly Qsys) system integration tool includes a component editor that allows you to import your own IP cores and package them as the Platform Designer (formerly Qsys) components for design reuse. Once packaged, the component can include a GUI for IP parameterization generated automatically by the component editor, a user-provided software driver, and simulation testbench.

Download Creating Qsys Components (PDF).

Q. Can I remotely update my FPGA over Ethernet?
A. Yes, the ability to update firmware over Ethernet is a common feature in today's embedded systems. Using the Nios II processor, you can extend the capability to updating the hardware image of one or more FPGAs.

Download Remote Configuration over Ethernet with the Nios II Processor (PDF).

Q. Can multiple Nios II processor cores be implemented in a single FPGA?
A. Yes, many developers implement multiple Nios II processors on a single FPGA. The Platform Designer (formerly Qsys) software provides a drag-and-drop interface to add and connect multiple processors, shared memories, and hardware mutex and mailbox peripherals. The Nios II processor EDS supports software development and debug of multiprocessor designs. Several embedded partners also provide RTOS and debugging tools to enhance development of multiprocessor designs.

Download Creating Multiprocessor Nios II Systems Tutorial (PDF).

Q. What hardware debug tools are available for Nios II processor development?
A. There are several debug tools that accelerate hardware development:

  • Signal Tap logic analyzer —The Signal Tap logic analyzer is a system-level debugging tool that captures and displays real-time signal behavior in a SoC, allowing you to observe interactions between hardware and software in system designs. Learn more about Signal Tap logic analyzer.

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Software Development Tools

Q. What software development tools are included with the Nios II processor?
A. A complete set of embedded software development tools including compiler, debugger, instruction set simulator, device drivers, hardware abstraction layer API, flash programmer, and related utilities are bundled together as the Nios II processor EDS. The Nios II processor EDS also contains the NicheStack TCP/IP network stack, and Micrium MicroC/OS-II real-time operating system.

Download Hardware Abstraction Layer (PDF).

Download Nios II Flash Programmer User Guide (PDF).

All hardware and software components needed to design a Nios II processor-based system (Nios II processor EDS, IP, Platform Designer (formerly Qsys) system integration tool, and Intel Quartus Prime design software) are available for free download from the Intel website and are included in Intel's development kits. Download Nios II design tools.

Q. Which embedded software tool providers support the Nios II processor?
A. The Nios II processor is supported by several commercial operating system, RTOS, debugger, middleware, and development tool providers. Learn more about software tools and software components.

Q. How do I develop software for a Nios II processor system?
A. The Nios II processor EDS collection of tools, utilities, libraries, and drivers contains everything needed to develop software applications for Nios II processor-based systems. The Nios II processor EDS includes:

All of these tools and libraries are included as part of the Nios II processor EDS, which is available for free download.

Download Nios II design tools.

Q. What do I need to know to write applications using the Nios II processor HAL?
A. Reference designs demonstrating the use of the Nios II processor HAL routines are included with the Nios II processor EDS; documentation for using the Nios II processor HAL is available for download from Intel's website.

Download Hardware Abstraction Layer (PDF).

Download HAL API Reference (PDF).

Q. What do I need to know to develop my own Nios II processor device drivers?
A. The Nios II processor EDS includes a library of peripheral device drivers. Documentation for creating your own device drivers is available for download from Intel's website.

Download Developing Device Drivers for the Hardware Abstraction Layer (PDF).

Q. What software utilities are included with the Nios II processor EDS?
A. Several command-line utilities come with the Nios II processor EDS to support project build, file conversion, download, debug, terminal, console, and GNU toolchain operations.

Learn more about development tools provided by Altera.

Q. What network support is provided for Nios II processor application development?
A. The Nios II processor EDS includes the NicheStack TCP/IP network stack, which is a small-footprint TCP/IP network stack providing IP, TCP, UDP, DHCP, ICMP, and ARP protocols using a standard sockets API.

Download Ethernet and the NicheStack TCP/IP Stack - Nios II Edition (PDF).

Q. Which RTOS support is provided in the Nios II processor EDS?
A. The Nios II processor EDS includes reference designs, source code, and an evaluation license for the Micrium MicroC/OS-II RTOS.

Download MicroC/OS-II Real-Time Operating System (PDF).

Q. What software tools are provided for developing interrupt service routines?
A. The Nios II processor HAL API provides facilities for developing custom interrupt service routines.

Download HAL API Reference (PDF).

Q. What software tools are provided for managing memory caches?
A. The Nios II processor HAL API provides facilities for managing cache memories.

Download Cache and Tightly-Coupled Memory (PDF).

Q. Can I develop software for multiple Nios II processors in a single FPGA?
A. Yes. Multiprocessor software application development and debug are supported by the Nios II processor IDE and Platform Designer (formerly Qsys).

Download Peripherals (PDF).

Download Creating Multiprocessor Nios II Systems Tutorial (PDF).

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Product Availability and Licensing

Q. What is the Intel FPGA IP Evaluation Mode feature and how does it work?
A. If you download an IP core (such as the Nios II processor) and do not already have the associated IP license, any designs you create operate in the Intel FPGA IP Evaluation Mode and allow you to do the following:

  • Simulate the behavior of the Nios II processor IP within your system
  • Verify the functionality of your design, as well as evaluate its size and speed quickly and easily
  • Generate time-limited device programming files for designs that include a Nios II processor
  • Program a device and verify your design in hardware

Intel FPGA IP Evaluation Mode hardware evaluation supports the following two modes of operation:

  • Tethered—requires a JTAG connection between your board and the host computer. If tethered mode is supported by all megafunctions in a design, the device can operate for a longer time or indefinitely
  • Untethered—the design runs for a limited time

Download AN 320: Using Intel® FPGA IP Evaluation Mode (PDF).

Q. What products are included with the Nios II processor and which require a license?
A. Refer to Table 1.

Table 1. Features and Licensing

Product Web Download Software Subscription
Nios II processor IP (1)  (1)
Nios II processor EDS    
NicheStack TCP/IP Network Stack, Nios II Edition    
Micrium MicroC/OS-II RTOS (1) (1)

 

Intel Quartus Prime design software    
Platform Designer (formerly Qsys)    
ModelSim*-Intel FPGA Edition software    
ModelSim-Intel FPGA Web Edition software    
JTAG download cable    
Development board    

Note:

  1. License sold separately.

Q. Do I need to purchase any licenses before I can begin development?
A. No. You can use all the Nios II processor licensed products for development; there are no restrictions other than the untethered time-limited operation.

Q. How do I obtain a license for the Nios II processor and related products?

  • Nios II processor IP—To obtain a license file for the Nios II processor, non-time-limited use, you must purchase the stand-alone Nios II processor core license (ordering code: IP-NIOS) or the Embedded IP Suite (ordering code: IPS-EMBEDDED). Contact your local Altera representative or Altera Tools Support to order today.
  • Micrium MicroC/OS-II RTOS—To obtain a license for the Micrium MicroC/OS-II RTOS, contact Micrium today.

Q. What do the Nios II processor product licenses entitle me to do?

  • Nios II processor IP—Once you purchase a Nios II processor license, you receive a perpetual, royalty-free license to ship systems that contain one or more Nios II processors targeted to Cyclone, Stratix, or Arria GX series FPGAs or SoCs. The license also includes one year of updates to the product. You can purchase additional 12-month maintenance subscriptions to ensure you always have the latest release. Please note that the Nios II/e (economy) processor is available at no charge and without a license.
  • Micrium MicroC/OS-II RTOS—Contact Micrium for license details.

Q. Can I get multiple Nios II processor licenses for our license server?
A. Yes, just as with any other Intel FPGA IP product, you may purchase as many license seats as you desire by using the IP-NIOS ordering code in conjunction with a FLOAT license for the Intel Quartus Prime software. These seats are listed at $495 each, but bulk and corporate discounts are negotiable. Contact customer service for details.

Q. Does Intel offer a Nios II processor license for ASIC development?
A. Yes. An ASIC license is available for Nios II processors. An ASIC optimized version of the Nios II processor core is available from the Synopsys* DesignWare STAR IP program. Please contact your Intel sales representative for details.

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Training and Technical Resources

Q. What training is available for Nios II processor developers?
A. Currently there are several training resources available:

  • Online training—Several training modules are available for free from the Intel FPGA training website. Learn more about training resources.
  • Instructor-led training—Intel provides training classes at many locations around the world. Learn more about training resources.
  • Tutorials—Intel's Nios II processor development kits include several tutorials and related reference designs. These tutorials are also available for download from the Nios II processor documentation web page.
  • Demonstrations on demand—While these modules are not intended as training, they provide a great overview of the design flow and tools used to develop Nios II processor systems. See online demonstrations.

Q. Are application-specific reference designs available?
A. Yes. There are several embedded reference designs posted on the Intel website to address specific applications such as image processing.

See design examples.

Q. What Nios II processor documentation is available and how can I get it?
A. The best place to find the latest Nios II processor documentation is on the Nios II processor documentation web page or search Altera.com for technical documentation.

Q. What other technical resources are available for Nios II processor developers?
A. There is a wealth of information on the web to help you learn more about designing with the Nios II processor:

  • Altera Forum—The Altera Forum is a community of over 20,000 Nios II processor developers and Altera users worldwide who share ideas, challenges, and reference designs.
  • Altera Wiki—The Altera Wiki provides a community resource where developers can post and maintain documentation and reference designs.
  • Design Contest Papers—This website contains the winning white papers from the annual Nios II processor design contest. It contains dozens of white papers on reference designs using the Nios II processor in applications with topics ranging from communications to robotics.

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Getting Started

Q. How hard is it to get started?
A. Getting started is simple. Learn more at our getting started page. Intel also provides development kits that contain an Intel FPGA and all the hardware and software necessary to begin your design. It takes about an hour from receiving the box to running your first program on the Nios II processor. Most of the time required is for software installation.