Intel® FPGA SDK for OpenCL™ version 18.0 includes key enhancements that deliver improved productivity and improved results.

New Fast Emulation

Intel FPGA SDK for OpenCL v18.0 includes improvements for the new fast emulator that delivers up to an order of magnitude faster emulation performance and is seamlessly integrated into the new Intel Code Builder for OpenCL API frameworks for easy execution. You can set up test vectors manually or through C++.

Intel® Stratix® 10 Device Support

You can now accelerate your applications using OpenCL on Intel Stratix® 10 devices. Featuring the revolutionary Intel® Hyperflex™ FPGA Architecture and built on the Intel 14 nm Tri-Gate process.

Fast and Incremental Compile

The fast compile option allows you to dramatically reduce the run time required to generate an FPGA programming file using the offline compiler with less aggressive compile settings that trade off a small amount of fMAX performance. This feature can be used to increase iterations per day while leaving you with the option to perform a full performance compile for the final implementation. For designs that consist of multiple kernels, a second incremental compile option is now available that will automatically identify the kernels that have changed and only recompile the changes.

What's New in Intel® FPGA SDK for OpenCL™ v17.1

Intel® FPGA SDK for OpenCL™ version 17.1 includes key enhancements that deliver improved productivity and improved results.

New Intel® Code Builder for OpenCL™ API Now with FPGA Support

Based on Intel’s world class software development framework technology, the Intel Code Builder for OpenCL API with FPGA kernel development framework provides a Microsoft* Visual Studio or Eclipse-based IDE that accelerates code development for developers who are new to FPGAs. This environment can be used to design, run, and validate OpenCL kernels for FPGA acceleration. Key features include:

  • New OpenCL project wizard
  • OpenCL syntax highlighting and code auto-completion features
  • Static FPGA resource usage analysis
  • System viewer and loop analysis
  • Host-level debugging
  • Offline compiler
  • Reports viewing
  • I/O and host channels support

New Fast Emulation

Based on Intel’s advanced compiler technology, Intel FPGA SDK for OpenCL v17.1 includes a new fast emulator that delivers up to an order of magnitude faster emulation performance and is seamlessly integrated into the new Intel Code Builder for OpenCL API frameworks for easy execution. You can set up test vectors manually or through C++.

Intel Stratix® 10 Device Support

You can now accelerate your applications using OpenCL on Intel Stratix® 10 devices. Featuring the revolutionary Intel Hyperflex™ FPGA Architecture and built on the Intel 14 nm Tri-Gate process, Intel Stratix 10 devices deliver 2X the performance gains over previous-generation, high-performance FPGAs with up to 70% lower power.

Host Channels

You can now significantly reduce the system latency of your systems using host channels that allows streaming data from the host to stream directly into the FPGA kernel through the PCIe* interface while bypassing the memory controller. The FPGA kernel can begin processing the data immediately and does not have to wait for the data transfer to complete. Host channels are supported in the OpenCL run time application programming interfaces (APIs) and include emulation support.

Fast Compile

Two new fast compile options are now available in Intel FPGA SDK for OpenCL v17.1 including “fast” and “incremental” compiles.  The fast compile option allows you to dramatically reduce the run time required to generate an FPGA programming file using the offline compiler with less aggressive compile settings that trade off a small amount of fMAX performance. This feature can be used to increase iterations per day while leaving you with the option to perform a full performance compile for the final implementation. For designs that consist of multiple kernels, a second incremental compile option is now available that will automatically identify the kernels that have changed and only recompile the changes.

OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos. 

† Comparison based on Stratix V vs. Stratix 10 using Quartus Prime Pro 16.1 Early Beta.  Stratix V Designs were optimized using 3 step optimization process of Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization in order to utilize Stratix 10 architecture enhancements of distributed registers in core fabric.  Designs were analyzed using Quartus Prime Pro Fast Forward Compile performance exploration tool.  For more details, refer to HyperFlex FPGA Architecture Overview White Paper: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01220-hyperflex-architecture-fpga-socs.pdf.  Actual performance users will achieve varies based on level of design optimization applied.  Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase.  For more complete information about performance and benchmark results, visit www.intel.com/benchmarks