The Intel® SoC FPGA Embedded Development Suite (SoC EDS) is a comprehensive tool suite for embedded software development on Intel SoC FPGAs. It comprises development tools, utility programs, and design examples to jump-start firmware and application software development.

SoC EDS also enables you to:

  • Leverage the power of ARM* Development Studio 5* (DS-5*) Intel SoC FPGA Edition to code, build, debug, and optimize your application
  • Expedite SoC FPGA embedded systems development with utility programs and run-time software
  • Jump start development with bare-metal and Linux* application examples

Intel SoC EDS is now available in Standard and Pro Editions. Both Standard and Pro Editions are available with a Free and a Paid license for ARM DS-5 Intel SoC FPGA Edition toolkit.

SoC EDS Standard - SoC EDS Standard includes extensive support for 28 nm SoC FPGA device families (Cylone® V SoC and Arria® V SoC).

SoC EDS Pro - SoC EDS Pro is optimized to support the advanced features in the next-generation SoC FPGA device families such as Intel Arria 10 SoC.

Note: Intel Arria 10 SoC is supported by both Standard and Pro Edition software but Intel Arria 10 SoC customers are encouraged to use the Pro Edition software to leverage device-specific optimizations.

Compare SoC EDS Standard and Pro Editions

 

Intel® SoC FPGA Embedded Development Suite


 ARM Development Studio 5 Intel SoC FPGA Edition Hardware Libraries Configuration Tools Examples

Powerful Eclipse IDE based on ARM DS-5 is power packed with features. Code, build, debug, and optimize in one IDE!

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Easy access to low-level hardware for configuration and control.

Intel FPGA-specific SoC configuration tools to improve productivity.

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Golden Hardware Reference Design (GHRD) for SoC FPGA development kits.  U-Boot, Linux, and bare metal reference examples to jump start your development.

What's New in SoC EDS v17.1

SoC EDS Standard Edition Toolchains
  • Baremetal GCC compiler tools version 6.2.0
  • Linux Linaro GCC compiler version 4.8.3 (4.8-2014.04)
  • ARM compiler 5 version 5.06u5
  • ARM compiler 6 version 6.7.1
  • ARM DS-5 Intel SoC FPGA Edition version 5.27.1
    • Support for Aarch64 Linux application debug
    • Cross triggering support with AMP debug
  • Linux Device Tree Generator (DTG)
  • Examples tested with Linux 4.1.33-LTSI Kernel
  • Golden System Reference Design (GSRD) available from rocketboards.org
    • Linux Kernel 4.1.33-LTSI
    • Angstrom v2015.12
  • Golden Hardware Reference Design (GHRD)
  • Arria 10 NAND reference design

SoC EDS Pro Edition Toolchains

  • Baremetal GCC compiler tools version 6.2.0
  • Linux Linaro GCC compiler version 4.8.3 (4.8-2014.04)
  • ARM compiler 5 version 5.06u5
  • ARM compiler 6 version 6.7.1
  • ARM DS-5 Intel SoC FPGA Edition version 5.27.1
    • Baremetal cheat sheets (tutorial)
    • Support for Aarch64 Linux application debug
    • Cross triggering support with AMP debug
  • Examples tested with Linux 4.1.33-LTSI Kernel
  • Linux Device Tree Generator (DTG)
    • Support added for TSE SGMII PCS
  • Golden System Reference Design (GSRD) available from rocketboards.org
    • Linux Kernel 4.1.33-LTSI
    • Angstrom v2015.12
  • Golden Hardware Reference Design (GHRD)
    • Arria 10 SoC Partial Reconfiguration
    • Arria 10 DisplayPort - Resolution updated from 640x480 to 1280x720

FPGA-Adaptive Debug

FPGA-adaptive debug, a powerful feature that gives a system-wide view of the SoC. This feature allows you to:

  • Cross-trigger between the HPS and the FPGA boundary with ease
  • Correlate FPGA and HPS events with high-resolution timestamps
  • Begin quick JTAG debugging with the low-cost Intel FPGA Download Cable II

 

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