Intel® Quartus® Prime Software Productivity Tools and Features

Intel® Quartus® Prime software provides everything you need to design with Intel FPGAs, SoCs, and CPLDs. It is a complete development package that comes with a user-friendly GUI and best-in-class technology to help you bring your ideas into reality. Learn more about the new and exciting features available in the Quartus Prime software.

Partial Reconfiguration

Partial reconfiguration of the FPGA offers several benefits - lower cost and power, increased flexibility - and enables new applications in segments such as data center and telecom. The Quartus Prime Pro Edition software features an intuitive flow with graphical user interface support for partial reconfiguration of Intel Arria® 10 FPGAs and SoCs. Designers can visually optimize the floorplan of the dynamic region that needs to be reconfigured in the chip planner. Constraints can be easily assigned using the LogicLock Plus feature in the Quartus Prime Pro Edition software.

Intel Qsys Pro System Integration Tool

Intel Qsys Pro tool is the next-generation system integration tool in the Quartus Prime Pro Edition software, and builds on the capabilities of Qsys, which is supported in the Quartus Prime Standard Edition software. Both Qsys and Qsys Pro system integration tool save significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems.

Synthesis

The synthesis engine in the Quartus Prime design software integrates a new front-end language parser, which allows designers to see improved language support for all IEEE register transfer level (RTL) languages. This includes expansive support for SystemVerilog-2005 and VHDL-2008. Support for all previously supported languages is also maintained. To learn more about how to use the synthesis tool, watch this training.

BluePrint Platform Designer

The BluePrint Platform Designer leverages the new Spectra-Q engine to explore a device’s peripheral architecture and efficiently assign interfaces. BluePrint prevents illegal pin assignments by performing fitter and legal checks in real time eliminating complex error messages and the need to wait for a full compile, speeding up your I/O design by 10X.

Using BluePrint Platform Designer for External Memory Interface Design

Watch this video to find out how to simplify placement of external memory interfaces with BluePrint Platform Designer.  

Quick Overview of the BluePrint Platform Designer’s Productivity Benefits 

The BluePrint Platform Designer leverages the new Spectra-Q engine to explore a device’s I/O interface architecture and efficiently assign interfaces. Watch this video to learn more about the productivity benefits of the BluePrint Platform Designer.

Fast & Easy I/O System Design with BluePrint 

In this training, learn about the BluePrint Platform Designer, an easy-to-use tool in the Quartus Prime software that uses the power of the Fitter to create a legal floorplan that used to take months in less than a week. Make guaranteed legal resource location assignments interface-by-interface instead of pin-by-pin to shorten your I/O planning cycle.

Note: BluePrint is supported in Arria® 10 and later FPGAs.

 

Physical Synthesis

Quartus Prime software includes physical synthesis optimization technology. Quartus Prime physical synthesis options are applied during the fitting stage of the compilation process and can be applied regardless of the synthesis tool used. Learn more about physical synthesis

Incremental optimizations

The incremental optimization capability in Quartus Prime Pro Edition software offers a faster methodology to converge to design sign-off. The traditional fitter stage is divided into finer stages for more control over the flow in Quartus Prime Pro Edition software. Timing analysis after each of these finer stages allows faster feedback and avoids full design iterations. Plan stage allows legal placement and clock planning, along with timing analysis on preliminary I/O and HSSI to FPGA fabric transfers. The place stage is now split into an early place stage (which is much faster than a full place, but with high correlation to final timing) and a final place stage. Route is split into Route and Post-Route stage for faster design convergence. Fine setup and hold optimizations, and full multi-corner analysis is performed in the post-route stage.

Early Placement

The incremental capability optimizations in Quartus Prime Pro Edition software offers a faster methodology to converge to design sign-off. Quartus Prime Pro Edition boosts the incremental optimization capability with a new early placement stage.

The traditional fitter stage is divided into finer stages for more control over the flow in Quartus Prime Pro Edition software.

  • Plan stage allows legal placement and clock planning, along with timing analysis on preliminary I/O and HSSI to FPGA fabric transfers
  • Place stage enables timing analysis before proceeding to the route stage. The place stage is now split into an early place stage and a final place stage
    • Perform timing analysis after early place
    • Chip planner provides visual view of early placement
  • Route is split into Route and Post-Route stage for faster design convergence.
    • 3 corner timing analysis after route, and 4-corner after post-route reduces compile time.
    • The post-route stage offers an ECO-like flow (Engineering Change Order) where setup and hold failures are automatically fixed. This has the added benefit of reducing compile time.
    • High-speed or low-power tile optimization is performed in Post-Route stage

To learn more about the new incremental optimization and per-stage compilation features of the Quartus Prime Pro edition see our free online class, Incremental Optimization with the Quartus Prime Pro Edition

Hybrid Placer

The Quartus Prime design software includes a new Hybrid Placer feature that uses advanced placement algorithms to speed up overall logic placement. The Hybrid Placer combines analytical and advanced annealing techniques for overall improved quality of results and a reduction in seed noise enabling faster timing closure.

Hybrid Placer

The Hybrid Placer, powered by Quartus Prime design software, is designed to dramatically scale productivity and time-to-market for the next-generation programmable devices. Watch to learn how the new hybrid placement technique provides you higher design performance and improved compile times.

Power Anaylzer

Our power analysis technology features Excel-based early power estimators (EPE) and the power analyzer tool in the Quartus Prime software. These power analysis tools give you the ability to estimate power consumption from early design concept through design implementation. Learn more about the Power Analyzer.

Design Space Explorer

The Quartus Prime software includes the next-generation Design Space Explorer (DSE), an easy-to-use design optimization tool, with an updated flow-oriented user interface, guiding users through the tool. DSE automates the process of finding the optimal collection of Quartus Prime software settings for a design to help you achieve timing closure, optimize area, and reduce power consumption. This updated tool also allows users to customize the Quality of Fit metric, which can be used to judge which exploration points are better. Learn more about the updated DSE tool.

TimeQuest Timing Analyzer

TimeQuest timing analyzer is the second generation, easy-to-use timing analyzer which leverages industry-standard Synopsys® Design Constraints (SDC) support to achieve accurate timing, resulting in faster timing closure. Watch this video to learn more.

  • Features ASIC-strength timing analysis tool
  • Provides native support for industry-standard SDC format
  • Supports complex clocking schemes
  • Provides improved performance
  • Enables easier ASIC prototyping
  • Provides easy-to-use GUI

View video      Support      Handbook (PDF)

System Console

System Console is a system-level debug tool that helps you to quickly and efficiently debug your FPGA design in real time using read-and-write transactions. Watch this video to get started!

  • Provides flexible system-level debug tool that helps designers quickly and efficiently debug their design while the design is running at full speed in an FPGA
  • Sends read-and-write system-level transactions into their system to help isolate and identify problems
  • Quickly checks system clocks and monitor reset states
  • Allows you to create your own custom verification or demonstration tool using graphical elements, such as buttons, dials, and graphs

View videos     Training     Handbook (PDF)     System Console web page

Signal Tap II Logic Analyzer

The Signal Tap™ II Logic Analyzer provides a system-level debugging tool that captures and displays real-time signal behavior.

  • Provides a system-level debugging tool that captures and displays real-time signal behavior
  • Gives you the ability to observe interactions between hardware and software in system designs
  • Supports the highest number of channels, sample depth, and clock speeds of any embedded logic analyzer
  • Gives you enhanced control over data sampling and display
  • Features a graphical interface

View video     Training     Support     Handbook (PDF)

JNEye

The state-of-the art JNEye link analysis tool allows you to evaluate high-speed serial link performance  quickly and easily. It is an ideal pre-design tool to help you understand how our solutions can fit your system requirements. 

ModelSim-Intel FPGA Edition

The ModelSim*-Intel® FPGA Edition software is a version of the ModelSim software targeted for Intel FPGA devices. The software supports Intel gate-level libraries and includes behavioral simulation, HDL testbenches, and Tcl scripting.

The Quartus Prime software interfaces with leading third-party EDA tools throughout the design flow. You can take advantage of various design and verification flows that you are already familiar with to maximize your efficiency.