Block-Based Design Flows1
The Intel® Quartus® Prime Pro Edition design software offers block-based design flows. They are of two types- the Incremental Block-Based Compilation and Design Block Reuse flows, which allow your geographically diverse development team to collaborate on a design.
Faster Timing Closure with Incremental Block-Based Compilation Flow
Team members can architect the design into segments, then individually develop and achieve timing closure on each partition of the design. Bringing the global design together is simple since each block maintains its placement and timing.
With these features, you can preserve, empty, or export the contents of a partition. A partition that has been preserved, emptied, or exported is called a design block. Using design blocks introduces the concepts of Block-Based Compilation and Design Block Reuse.
Incremental Block-Based Compilation is preserving or emptying a partition within a project. This works with core partitions and requires no additional files or floor planning. The partition can be emptied, preserved at Source, Synthesis, and Final snapshots.
Easier Collaboration with Design Block Reuse Flow
The Design Block Reuse flow enables you to reuse a block of a design, in a different project, by creating, preserving, and exporting a partition. With this feature, you can expect a clean hand off, of timing-closed modules between different teams. It also gives you the flexibility of placing timing-closed blocks, pre-built components or even 3rd party intellectual property (IP).
Two types of block reuse are supported in this flow - core logic partition and periphery partition. The Periphery Reuse flow allows you to reuse a placed and routed periphery (including I/O, HSSIO, PCIe*, phase-locked loops (PLLs), as well as core resources) and leave an empty (flexible) development area open for other designers. The empty area is defined by a special type of partition that creates a hole in the periphery. This hole can be developed later by another team.
- Block-Based Design User Guide
- AN 839: Design Block Reuse Tutorial and Design File (zip)
- AN 847: Signal Tap Tutorial with Design Block Reuse and Design File (zip)
Intel FPGA training classes on block-based design flows are as follows:
- Incremental Block-Based Compilation in the Intel Quartus Prime Pro Software: Introduction
- Incremental Block-Based Compilation in the Intel Quartus Prime Pro Software: Design Partitioning
- Incremental Block-Based Compilation in the Intel Quartus Prime Pro Software: Timing Closure & Tips
- Design Block Reuse in the Intel Quartus Prime Pro Software
1This feature has some known limitations. Refer to Why I can't compile Intel Stratix 10 partitions exported from another project with a different top level and Internal Error: Sub-system: PTI, File: /quartus/tsm/pti/pti_tdb_builder.cpp