The Interface Planner explores a device’s peripheral architecture and efficiently assign interfaces. The Interface Planner prevents illegal pin assignments by performing fitter and legal checks in real time eliminating complex error messages and the need to wait for a full compile thereby speeding up your I/O design.
Watch this video to find out how to simplify placement of external memory interfaces with the Interface Planner.
The Interface Planner explores a device’s I/O interface architecture and efficiently assign interfaces. Watch this video to learn more about the productivity benefits of the Interface Planner.
In this training, learn about the Interface Planner, an easy-to-use tool in the Intel® Quartus® Prime software that uses the power of the Fitter to create a legal floorplan that used to take months in less than a week. Make guaranteed legal resource location assignments interface-by-interface instead of pin-by-pin to shorten your I/O planning cycle.
Note: The Interface Planner is supported in Intel Arria® 10 FPGAs and later devices.