Platform Designer (formerly Qsys)

The Platform Designer (formerly Qsys) is the next-generation system integration tool in the Intel® Quartus® Prime software. The Platform Designer saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. The Platform Designer utilizes a powerful hierarchical framework to offer fast response times for interconnecting large systems, while also providing support for blackbox entities. This enables Platform Designer to provide fast response times while opening systems and creating new connections by regenerating or operating on IP blocks that have changed. The new Platform Designer tool also supports a variety of design entry methods, such as register transfer level (RTL) languages, block-based design entry, to schematic entry, and black boxes.

Platform Designer in the Pro Edition of the Intel Quartus Prime software, expands the ease of use, flexibility, and performance of the standard Platform Designer system design tool. Our training course, System Design with Platform Designer Pro, explores the differences between the Intel Quartus Prime Standard and Pro Edition software versions of the tools, focusing on Platform Designer support for generic components in the Pro edition - the idea that every component in a system design is essentially a blackbox defined by its interface and signal connections to the rest of the system. Separating components from the system design in this way helps with team-based design and version control. You'll learn about the new features of the tool that support generic components and how to validate the integrity of a system.

In the Intel Quartus Prime Pro Edition software v17.1, the Platform Designer supports the new features that greatly help with design portability. HLS integration which is the ability for the user to add .cpp files to Platform Designer and define IP components around them. System Verilog Interface Support which is the ability for the user to incorporate IP components which use SystemVerilog interfaces into Platform Designer systems. More details about these new features can be found in the Creating a System with Qsys Pro section in volume 1 of the Intel Quartus Prime Pro Edition Handbook. Also, please watch the new Platform Designer overview video that walks through how to use the tool.

Platform Designer (Standard / Platform Designer Pro) Platform Designer (Standard) / Platform Designer Pro Advantages
Faster development
  • Easy-to-use GUI interface enables quick integration between IP functions and subsystems
  • Automatic generation of interconnect logic (address/data bus connections, bus width matching logic, address decoder logic, arbitration logic, etc.)
  • Availability of plug-and-play Qsys-compliant IP. (Note: Platform Designer-Pro compliance is not available for all IP)
  • Support mixing of different industry-standard interfaces including Avalon®, ARM* AMBA* AXI*, AMBA APB*, and AMBA AHB* interfaces
  • Automatic HDL generation of your system
  • Hierarchical design flow enables scalable designs, team-based design, and maximizes design reuse
  • Migration flow to Platform Designer (does not apply to Platform Designer Pro) for SOPC Builder designs (view demo)
Faster timing closure
  • High-performance Platform Designer (Standard) interconnect based on the NoC architecture and automatic pipelining delivers higher performance compared to SOPC Builder’s system interconnect fabric (view demo)
  • Ability to control the aggressiveness of automatic pipelining to meet fMAX and latency system requirements
Faster verification
  • Ability to start your simulation faster with automatic testbench generation and by using the verification IP suite
  • Faster board bring-up with System Console by sending read and write transactions into a live system (view demo)

Webcasts

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Conquer FPGA Design Complexity with System-Level Integration

  • Learn how the Platform Designer can improve your productivity, saving you valuable development time in your next and future FPGA designs.

View webcast

Demonstrations

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AMBA AXI and Altera Avalon Interoperation Using Platform Designer (Standard)

See how seamless it is to integrate IP components with AMBA AXI interfaces with Avalon interfaces using the Platform Designer (Standard).

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View Video

Increase Interconnect Performance with Platform Designer (Standard)

See how you can improve the performance of the Platform Designer (Standard) interconnect with automatic register pipelining.

View demo
View Video

Board Bring-Up with System Console

  • See how you can bring up your board with a few simple checks
  • Learn how to quickly isolate issues by checking your system’s resets and clocks, and by performing simple address-based read and write transactions

View demo

View Video

Building a Custom GUI with System Console

  • See how you can build your own custom GUI to debug and monitor your system
  • Learn how to add different graphical elements to control and monitor your system

View demo

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase.  For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.