Qsys - System Integration Tool

The Qsys Pro system integration tool saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems.

Qsys Pro utilizes a powerful new hierarchical framework to offer much faster response time for interconnecting large systems, while also providing support for blackbox entities. Additionally, Qsys Pro retains the high l evels ofease of use of "classic Qsys". Qsys Pro is available only in Quartus® Prime Pro Edition software.

Qsys is the next-generation SOPC Builder tool powered by a new FPGA-optimized network-on-a-chip (NoC) technology delivering higher performance, improved design reuse, and faster verification compared to SOPC Builder. Qsys is available in Quartus Prime Standard Edition software.

Qsys / Qsys Pro Benefits Qsys / Qsys Pro Advantages
Faster development
  • Easy-to-use GUI interface enables quick integration between IP functions and subsystems
  • Automatic generation of interconnect logic (address/data bus connections, bus width matching logic, address decoder logic, arbitration logic, etc.)
  • Availability of plug-and-play Qsys-compliant IP. (Note: Qsys-Pro compliance is not available for all IP)
  • Support mixing of different industry-standard interfaces including Avalon®, ARM® AMBA® AXITM, AMBA APBTM, and AMBA AHBTM interfaces
  • Automatic HDL generation of your system
  • Hierarchical design flow enables scalable designs, team-based design, and maximizes design reuse
  • Migration flow to Qsys (does not apply to Qsys Pro) for SOPC Builder designs (view demo)
Faster timing closure
  • High-performance Qsys interconnect based on the NoC architecture and automatic pipelining delivers up to 2X higher performance compared to SOPC Builder’s system interconnect fabric (view demo)
  • Ability to control the aggressiveness of automatic pipelining to meet fMAX and latency system requirements
Faster verification
  • Ability to start your simulation faster with automatic testbench generation and by using the verification IP suite
  • Faster board bring-up with System Console by sending read and write transactions into a live system (view demo)

Webcasts

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Conquer FPGA Design Complexity with System-Level Integration

  • Learn how Qsys can improve your productivity, saving you valuable development time in your next and future FPGA designs.

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Easily Create PCIe-Based Designs for FPGAs

  • Learn how easy it is to build a PCIe-based design using Qsys
  • Learn about the advantages of the optimized PCI Express® (PCIe®) memory-mapped IP core

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Demonstrations

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AMBA AXI and Altera Avalon interoperation using Qsys

See how seamless it is to integrate IP components with AMBA AXI interfaces with Avalon interfaces using Qsys.

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Increase Interconnect Performance with Qsys

See how you can improve the performance of the Qsys interconnect with automatic register pipelining.

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Faster Board Bring-Up with System Console

  • See how you can bring up your board faster with a few simple checks
  • Learn how to quickly isolate issues by checking your system’s resets and clocks, and by performing simple address-based read and write transactions

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Building a Custom GUI with System Console

  • See how you can build your own custom GUI to debug and monitor your system
  • Learn how to add different graphical elements to control and monitor your system

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