The Qsys Pro system integration tool saves significant time and effort in the FPGA design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems.
Qsys Pro utilizes a powerful new hierarchical framework to offer much faster response time for interconnecting large systems, while also providing support for blackbox entities.
This enables Qsys Pro to provide 100x faster response time while opening systems and creating new connections by regenerating or operating on IP blocks that have changed. The new Qsys Pro tool also supports a variety of design entry methods, such as register transfer level (RTL) languages, block-based design entry, to schematic entry, and black boxes.
Qsys Pro, available only in the Pro Edition of the Quartus Prime software, expands the ease of use, flexibility, and performance of the standard Qsys system design tool. Our training course, System Design with Qsys Pro, explores the differences between the two tools, focusing on Qsys Pro's support for generic components - the idea that every component in a system design is essentially a blackbox defined by its interface and signal connections to the rest of the system. Separating components from the system design in this way helps with team-based design and version control. You'll learn about the new features of the tool that support generic components and how to validate the integrity of a system.