Intel® Quartus® Prime design software, powered by the Spectra-Q™ engine, is primed to improve your productivity as you target our next generation devices with multi-million logic elements. Built on the success of Quartus II software, Quartus Prime software with the Spectra-Q engine consists of a new set of faster and more scalable algorithms, a new hierarchical database infrastructure and a new unified compiler technology.
Intel Quartus Prime software is available in three editions based on your design requirements: Pro, Standard, and Lite Edition.
- Quartus Prime Pro Editon–The Quartus Prime Pro Edition is optimized to support the advanced features in Intel's next-generation FPGAs and SoCs, starting with the Arria® 10 device family.
- Quartus Prime Standard Edition–The Quartus Prime Standard Edition includes the most extensive support for Intel's latest device families and requires a subscription license.
- Quartus Prime Lite Edition–The Quartus Prime Lite Edition provides an ideal entry point to Intel's high-volume device families and is available as a free download with no license file required
To compare the different features available in each edition, visit this page. Download today and experience Quartus Prime 16.1 delivery of unbeatable performance with a full speed grade advantage for Arria 10 devices.
Intel FPGA Intellectual Property
In addition to these new exciting capabilities, the v16.1 release of Intel FPGA intellectual property (IP) features new additions and feature enhancements to the MegaCore® function portfolio. Click on the What's New in IP web page to learn about some of the exciting new features.
Partial reconfiguration of the FPGA offers several benefits and enables new applications. Quartus Prime Pro Edition v16.1 features an intuitive flow with graphical user interface support for partial reconfiguration of Arria 10 FPGAs and SoCs. Designers can visually optimize the floorplan of the dynamic region that needs to be reconfigured in the chip planner. Constraints can be easily assigned using the LogicLock Plus feature in Quartus Prime Pro Edition. Watch this video to learn more.
The key benefits of partial reconfiguration are:
- Lower cost
- Smaller board footprint
- Lower power
Application examples are shown in the simplified illustrations below. Figure A shows an application for algorithm acceleration, and Figure B shows a telecom application in optical networking. In both cases, the FPGA is reconfigured to implement different functions – a different algorithm in the case of algorithm acceleration, or a different client protocol in the telecom application (an optical networking muxponder). The key benefit here is that the rest of the FPGA continues to function.
The incremental capability optimizations in Quartus Prime Pro Edition software offers a faster methodology to converge to design sign-off. The 16.1 release of Quartus Prime Pro Edition boosts the incremental optimization capability with a new early placement stage.
The traditional fitter stage is divided into finer stages for more control over the flow in Quartus Prime Pro Edition software.
- Plan stage allows legal placement and clock planning, along with timing analysis on preliminary I/O and HSSI to FPGA fabric transfers
- Place stage enables timing analysis before proceeding to the route stage. The place stage is now split into an early place stage and a final place stage
- Perform timing analysis after early place
- Chip planner provides visual view of early placement
- Route is split into Route and Post-Route stage for faster design convergence.
- 3 corner timing analysis after route, and 4-corner after post-route reduces compile time.
- The post-route stage offers an ECO-like flow (Engineering Change Order) where setup and hold failures are automatically fixed. This has the added benefit of reducing compile time.
- High-speed or low-power tile optimization is performed in Post-Route stage
To learn more about the new incremental optimization and per-stage compilation features of the Quartus Prime Pro edition see our free online class, Incremental Optimization with the Quartus Prime Pro Edition.
The new Qsys Pro system integration tool in the Pro Edition software retains the powerful functionality of Qsys, but with a new hierarchical framework of Spectra-Q engine. This enables Qsys Pro to provide 100x faster response time while opening systems and creating new connections by regenerating or
operating on IP blocks that have changed. The new Qsys Pro tool also supports a variety of design entry methods, such as register transfer level (RTL) languages, block-based design entry, to schematic entry, and black boxes.
Qsys Pro, available only in the Pro Edition of the Quartus Prime software, expands the ease of use, flexibility, and performance of the standard Qsys system design tool. Our training course, System Design with Qsys Pro, explores the differences between the two tools, focusing on Qsys Pro's support for generic components - the idea that every component in a system design is essentially a blackbox defined by its interface and signal connections to the rest of the system. Separating components from the system design in this way helps with team-based design and version control. You'll learn about the new features of the tool that support generic components and how to validate the integrity of a system.
The BluePrint Platform Designer explores a device’s peripheral architecture and efficiently assigns interfaces. BluePrint prevents illegal pin assignments by performing fitter and legal checks in real time. This flow eliminates complex error messages and the need to wait for a full compile, thereby speeding up your I/O design by 10X. To learn more about the BluePrint Platform Designer, watch these videos.
In this training, you will learn about the new incremental optimization and per-stage compilation features of the Quartus Prime Pro edition. These are features enabled by the new Spectra-Q engine designed to help customers achieve maximum productivity while compiling and optimizing their FPGA designs. We will explain the benefits of using these new features and how to enable them in the Quartus Prime Pro design software.
Qsys Pro, available only in the Pro Edition of the Quartus Prime software, expands the ease of use, flexibility, and performance of the standard Qsys system design tool. This training explores the differences between the two tools, focusing on Qsys Pro's support for generic components, the idea that every component in a system design is essentially a blackbox defined by its interface and signal connections to the rest of the system. Separating components from the system design in this way helps with team-based design and version control. You'll learn about the new features of the tool that support generic components and how to validate the integrity of a system.
In this training, learn about the BluePrint Platform Designer, an easy-to-use tool in the Quartus Prime software that uses the power of the Fitter to create a legal floorplan that used to take months in less than a week. Make guaranteed legal resource location assignments interface-by-interface instead of pin-by-pin to shorten your I/O planning cycle. Note: Blueprint is supported in Arria 10 and later FPGAs.
The Spectra-Q synthesis engine integrates a front-end language parser into the Quartus Prime software. With the front-end parser, designers will see improved language support for all IEEE RTL languages, including more support for SystemVerilog-2005 and VHDL-2008. Support for all previously supported languages is also maintained. To learn more about how to use the Spectra-Q Synthesis Tool, watch this video.
Watch this video to find out how to simplify placement of external memory interfaces with BluePrint Platform Designer.
The BluePrint Platform Designer leverages the Spectra-Q engine to explore a device’s I/O interface architecture and efficiently assign interfaces. Watch this video to learn more about the productivity benefits of the BluePrint Platform Designer.