Intel® Quartus® Prime design software is primed to improve your productivity as you target our next-generation devices with multi-million logic elements. Built on the success of the Quartus II software, the Quartus Prime software consists of a new set of faster and more scalable algorithms, a new hierarchical database infrastructure, and a new unified compiler technology.
Intel Quartus Prime software is available in three editions based on your design requirements: Pro, Standard, and Lite Edition.
- Quartus Prime Pro Edition–The Quartus Prime Pro Edition is optimized to support the advanced features in Intel's next-generation FPGAs and SoCs, starting with the Intel Arria® 10 device family.
- Quartus Prime Standard Edition–The Quartus Prime Standard Edition includes the most extensive support for Intel's latest device families and requires a subscription license.
- Quartus Prime Lite Edition–The Quartus Prime Lite Edition provides an ideal entry point to Intel's high-volume device families and is available as a free download with no license file required
To compare the different features available in each edition, visit this page. Download today and experience Quartus Prime 17.0 delivery of unbeatable performance with a full speed grade advantage for Arria 10 devices.
In addition to these new exciting capabilities, the v17.0 release of Intel FPGA intellectual property (IP) features new additions and feature enhancements to the Intel FPGA IP function portfolio. Click on the What's New in IP web page to learn about some of the exciting new features.
Faster Timing Closure with Incremental Block-Based Compilation Flow
The Quartus Prime Pro Edition design software v17.0 offers the new Incremental Block-Based Compilation and Design Block Reuse flows, which allow your geographically diverse development team to collaborate on a design. Team members can architect the design into segments, then individually develop and achieve timing closure on each partition of the design. Bringing the global design together is simple since each block maintains its placement and timing.
With these features, you can preserve, empty, or export the contents of a partition. A partition that has been preserved, emptied, or exported is called a design block. Using design blocks introduces the concepts of Block-Based Compilation and Design Block Reuse.
Incremental Block-Based Compilation is preserving or emptying a partition within a project. This works with core partitions and requires no additional files or floor planning. The partition can be emptied, preserved at Source, Synthesis, and Final snapshots.
Easier Collaboration with Design Block Reuse Flow
The Quartus Prime design software v17.0 offers the new Design Block Reuse flow, which enables a user to reuse a block of a design, in a different project, by creating, preserving, and exporting a partition. With this feature, you can expect a clean hand off, of timing-closed modules between different teams. It also gives you the flexibility of placing timing-closed blocks, pre-built components or even 3rd party IP.
Two types of block reuse are supported in this flow - core logic partition and periphery partition. The Periphery Reuse flow allows you to reuse a placed and routed periphery (including I/O, HSSIO, PCIe*, phase-locked loops (PLLs), as well as core resources) and leave an empty (flexible) development area open for other designers. The empty area is defined by a special type of partition that creates a hole in the periphery. This hole can be developed later by another team.
The incremental optimization capability in the Quartus Prime Pro Edition software offers a faster methodology to converge to design sign-off with a new Early Placement stage.
The traditional fitter stage is divided into finer stages for more control over the flow in the Quartus Prime Pro Edition software:
- Plan stage allows legal placement and clock planning, along with timing analysis on preliminary I/O and HSSI to FPGA fabric transfers
- Placement stage enables timing analysis before proceeding to the Route stage. The Placement stage is split into an Early Placement stage and a final placement stage:
- Perform timing analysis after the Early Placement stage
- Chip planner provides a visual view of the Early Placement stage
- Route is split into Route and Post-Route stage for faster design convergence.
- 3-corner timing analysis after route, and 4-corner timing analysis after post-route reduces compile time.
- The post-route stage offers an Engineering Change Order (ECO)-like flow where setup and hold failures are automatically fixed, thus reduces compile time.
- High-speed or low-power tile optimization is performed in the Post-Route stage.