Intel® Quartus® Prime software v17.1 is about supercharging your design with all the new features and capabilities that the Intel Quartus Prime Pro Edition software has to offer. There are improvements made across the three key areas that designers care about the most—performance, productivity, and usability.
Intel Stratix® 10 MX, SX, and GX Device Support
Intel Quartus Prime Pro Edition software v17.1 supports Intel Stratix® 10 MX, SX, and GX devices.
Intel Stratix 10 GX devices are designed to meet the high-performance demands of high-throughput systems with up to 10 TFLOPS of floating-point performance and transceiver support up to 28.3 Gbps for chip-module, chip-to-chip, and backplane applications.
Intel Stratix 10 SX SoCs feature a hard processor system with a 64 bit quad-core ARM* Cortex*-A53 processor available in all densities in addition to all the features of Intel Stratix 10 GX devices.
Intel Stratix 10 MX devices combine the programmability and flexibility of Intel Stratix 10 FPGAs and SoCs with the 3D stacked high-bandwidth memory 2 (HBM2) in a single package. Intel Stratix 10 MX FPGAs support both H- and E- transceiver tiles.
With the revolutionary Intel HyperFlex™ FPGA Architecture, Intel Stratix 10 devices deliver performance gains over previous-generation high-performance FPGAs. Learn more about the Intel HyperFlex FPGA Architecture and Intel Stratix 10 devices. Watch all the latest Intel Stratix 10 FPGA videos on the Stratix 10 Demo Videos page.
Intel Quartus Prime Software Hyper-Aware Design Flow and Using Fast Forward Compile for the Intel HyperFlex FPGA Architecture are two updated training classes that you can take to understand the Intel HyperFlex FPGA Architecture specifics. To learn how to leverage the Intel HyperFlex FPGA Architecture features, watch the new videos on the Intel Quartus Prime software support page.
Intel HLS Compiler
You can now accelerate FPGA development with C++ using the new Intel HLS Compiler. The Intel HLS Compiler is a high-level synthesis (HLS) tool that takes in untimed C++ as input and generates production-quality register transfer level (RTL) code that is optimized for Intel FPGAs. For more details, visit the Intel HLS Compiler web page. Note that the Intel HLS Compiler supports all editions of Intel Quartus Prime software v17.1.
Improved Block-Based Design Flows
The block-based design flows—Design Block Reuse and Incremental Block-Based Compilation—are now supported in Intel Stratix 10, Intel Arria® 10, and Intel Cyclone® 10 device families. There are new features with each of these flows that are described in the Block-Based Design Flows section in volume 1 of the Intel Quartus Prime Pro Edition Handbook. There is also a new tutorial for the design reuse flow on the block-based design flow homepage.
Partial Reconfiguration allows you to reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function. With Intel Quartus Prime Pro Edition software v17.1, there are three key Partial Reconfiguration features for Intel Stratix 10 and Intel Arria 10 device families:
- Hierarchical partial reconfiguration
- Simulation of partial reconfiguration
- Simultaneous debug of static and dynamic partial reconfiguration regions with the Signal Tap logic analyzer
Learn more about each of these features on the Partial Reconfiguration page.
Logic Equivalency Checking
Logic Equivalency Checking (LEC) is a new feature supported with the Intel HyperFlex FPGA Architecture in Intel Quartus Prime Pro Edition software v17.1. It proves that the post Intel HyperFlex FPGA Architecture-optimized netlist is equivalent to the post fitter netlist. A third-party tool that you can refer to is the 360-EC FPGA solution by OneSpin.
Platform Designer (formerly Qsys)
With Intel Quartus Prime Pro Edition software v17.1, you can now add C++ (.cpp) files to the Platform Designer and define intellectual property (IP) components around them. You can also incorporate IP components that use SystemVerilog Interfaces into Platform Designer systems. More details on all these features are available in the Creating a System in Qsys Pro section in volume 1 of the Intel Quartus Prime Pro Edition Handbook and the Platform Designer (formerly Qsys) web page.
Intel Stratix 10 Device Post-Fit Tap for Faster Debug Iterations
Intel Stratix 10 FPGA designs will now have the ability to change the Signal Tap logic analyzer probe points without re-compilation, resulting in faster debug iterations. Therefore, if only the probes are changing in your design, you do not need to recompile your design and can simply route the probe points, which saves you significant time. Read more in the Design Debugging with the Signal Tap Logic Analyzer section in volume 3 of the Intel Quartus Prime Pro Edition Handbook.
Design Partition Planner
The Design Partition Planner in Intel Quartus Prime Pro Edition software v17.1 allows you to view design connectivity and hierarchy as well as assist you in creating, optimizing, and gauging the quality of your design partitions. Read more in the Design Partition Guidelines section in volume 1 of the Intel Quartus Prime Pro Edition Handbook.
Software Tools on the Cloud
With Intel Quartus Prime Pro Edition software v17.1, you can accelerate your applications using Intel FPGA programming tools on the cloud to program FPGAs in a high-performance computing environment provided by Nimbix. Learn more on the Cloud Services web page.
Some features have now been enhanced from a usability standpoint in Intel Quartus Prime Pro Edition software v17.1. Some of them are as follows:
- Redesigned IP upgrade dialog box
- Logic lock regions. There is a new Chip Planner training class that you can take to understand floorplanning and logic lock regions.
- For additional features, please refer to the Intel Quartus Prime software support page.