DSP Builder for Intel® FPGAs is a digital signal processing (DSP) design tool that allows push-button HDL generation of DSP algorithms directly from MathWorks* Simulink* environment. This tool allows you to design algorithm, set desired data rate, clock frequency, and device offering accurate bit and cycle simulation, synthesizing fixed- and floating-point optimized HDL, auto-verify in ModelSim*- Intel FPGA software, and auto-verify/co-simulate on hardware.
Intel HLS Compiler increases designer productivity by raising the design entry abstraction level from register transfer level (RTL) to untimed C++. The tool shortens development time through accelerated verification and employs device-specific optimization to deliver production quality RTL that can be integrated with Qsys and into the Intel Quartus® Prime software.
With the Intel FPGA SDK for Open Computing Language (OpenCL™), you develop FPGA designs in C using a high-level software flow. You can emulate your OpenCL C accelerator code on an x86-based host in seconds, get a detailed optimization report with specific algorithm pipeline dependency information, or prototype the accelerator kernel on a virtual FPGA fabric in minutes. After you have fine-tuned your kernel code, you can compile the design.