Intel® HLS Compiler is a high-level synthesis (HLS) tool that takes in untimed C++ as input and generates production-quality register transfer level (RTL) that is optimized for Intel FPGAs. This tool accelerates verification time over RTL by raising the abstraction level for FPGA hardware design. Models developed in C++ are typically verified orders of magnitude faster than RTL.


  • Uses untimed ANSI C++ as the golden design source
  • Allows you to quickly explore multiple architectures through high-level directives
  • Simplifies tool usage by inferring design intent from high-level constraints
  • Supports verification of RTL by comparison with the original C++ source model
  • Generates reusable intellectual property (IP) for system integration using the Qsys system integration tool
  • Supports inference of streaming, memory mapped or wire interfaces
  • Performs device-specific timing-driven schedule optimization and technology mapping for Intel FPGAs
  • Supports a software compiler use model and industry standards including ac_int data types

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Intel® HLS Compiler