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From this course, you will learn how to use the Intel HLS Compiler to synthesize, optimize, and verify design intellectual property (IP) cores for Intel FPGAs. We will first discuss the benefits of high-level synthesis (HLS) and then talk about the Intel HLS Compiler features. You will learn how to use the compiler options, the generated reports, and the final generated files to integrate the IP cores within an Intel Quartus® Prime design software project. Lastly, you will learn how to effectively optimize your IP cores using the generated reports.

At Course Completion

You will be able to:

  • Use the Intel HLS Compiler to synthesize Intel Quartus® Prime design software compatible IP cores
  • View the Intel HLS Compiler generated reports to debug and optimize your IP cores
  • Co-simulate your HLS IP cores using an RTL simulator with a software testbench
  • Integrate the HLS-generated IP cores within an FPGA design
  • Use pragmas to control the HLS compilation
  • Effectively pipeline loops
  • Optimize local memory architecture
  • Effectively use various data types and math support features 
  • Understand the limitations of the compiler
 
  Libraries   Description Download
RAND
Provides an application programming interface (API) that allows you to generate random floats and integers inside a HLS component.
Coming soon!
MATH Includes all math functions from the math.h library for your OS Included with Intel® Quartus® Prime design software v17.1
Design Examples Description Download
QRD
This design example factors an input matrix into a Q matrix (which is ortho-normal) and an R matrix (which is upper triangular) using the popular Modified Gram Schmidt (MGS) algorithm. This design is runtime-parameterizable, so the size of the matrix to factor can be specified when the component is invoked. Before compiling the design, users can specify the maximum matrix size that the component can handle. It illustrates a number of HLS practices including memory banking for parallel access, streaming interfaces, and more.
Coming soon!
Document Description Download
Product Brief Highlights the key features of the Intel HLS Compiler.  Download
Image Processing White Paper Presents the design flow enabled by the compiler while displaying an image procesing design example.   Download
Getting Started Guide Shows how to initialize your high-level synthesis compiler environment. Also includes design examples and tutorials to demonstrate ways to effectively use the compiler. Download
User Guide Provides instructions on synthesizing, verifying,
and simulating IP cores that you design for Intel FPGA products.
Download
Reference Manual Provides information about the high-level synthesis (HLS) component design flow, including command options and other programming elements you can use in your component code. Download
Best Practices Guide Offers tips and guidance on how to optimize your component design using information provided by the HLS compiler. Download
Quick Reference Guide Provides a list of command lines, pragmas, and directives to get started on your design. Coming Soon!
Optimizing QRD Decomposition White Paper Describes a QR decomposition implementation using the Intel HLS compiler. This document intends to help software engineers who are new to high-level synthesis to effectively use the HLS compiler by showing how HLS optimizations may be applied to a real piece of code.
 
Coming soon!