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Get late-breaking information about the Intel® HLS Compiler included with Intel Quartus® Prime design suite v18.0.

Get up and running with the Intel HLS Compiler by learning how to initialize your compiler environment and reviewing the various design examples and tutorials provided with the Intel HLS Compiler.

Go through the entire development flow of your component from creating your component and testbench up to integrating your component intellectual property (IP) into a larger system with the Intel Quartus Prime design software.

Find details on Intel HLS Compiler command options, header files, pragmas, attributes, macros, declarations, arguments, and template libraries.

Improve the area utilization and performance of the components that you develop with the Intel HLS Compiler by applying the techniques and practices described in this guide.

Get a brief summary of Intel HLS Compiler declarations and attributes on a two-sided page.

  Libraries   Description
RAND
Provides an application programming interface (API) that allows you to generate random floats and integers inside a high-level synthesis (HLS) component.
MATH Includes all math functions from the math.h library for your operating system (OS).
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Design Examples Description
QRD
Factors an input matrix into a Q matrix (which is ortho-normal) and an R matrix (which is upper triangular) using the popular Modified Gram Schmidt (MGS) algorithm. This design is runtime-parameterizable, so the size of the matrix to factor can be specified when the component is invoked. Before compiling the design, users can specify the maximum matrix size that the component can handle. It illustrates a number of HLS practices including memory banking for parallel access, streaming interfaces, and more.
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Discover the key features and benefits of the Intel® HLS Compiler.

Learn about the design flow enabled by the Intel® HLS Compiler through an image processing example.

Learn how to optimize your code for the Intel HLS Compiler by optimizing a matrix QR decomposition application.

Learn how to use your Eclipse* IDE to develop for the Intel® HLS Compiler

Register for a Training Class

 
In the class, you will learn how to use the Intel® HLS Compiler to synthesize, optimize, and verify design components for Intel FPGAs. We will first discuss the benefits of HLS then talk about features of the Intel HLS Compiler. You will learn how to use the compiler options, the generated reports, and the final generated files to integrate the IP within an Intel Quartus® design software project. Lastly you will learn how to effectively optimize your IP using the generated reports.

 

At Course Completion, you will be able to:

  • Use the Intel HLS Compiler to synthesize an Intel Quartus®-compatible component
  • View reports to debug and optimize the component
  • Co-simulate your HLS component using an RTL simulator with a software testbench
  • Integrate the HLS-generated component within an FPGA design
  • Understand the various interfaces available and be able to select the optimal one for various types of components
  • Effectively use various data types and math support features
  • Understand how the compiler pipelines loop
 
In the class, you will learn how to use advanced techniques using the Intel HLS Compiler to create an optimized IP for Intel FPGAs. We will cover using recommended techniques to improve loop pipelining performance. We will discuss how the Intel HLS compiler generates and optimizes local memory architecture as well as how to best guide the compiler to create never-stall local memories. Lastly, we will use several real-life design examples to demonstrate the optimization flow.

 

At Course Completion, you will be able to:

  • Use the HTML reports generated by the Intel HLS Compiler to locate performance bottlenecks in a component
  • Effectively pipeline loops by removing data and memory dependencies
  • Use pragmas to control HLS loop performance
  • Optimize local memory architecture
  • Use all the optimization tools available in the Intel HLS Compiler to create a high-performance FPGA IP

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