The 18.0 release of Intel® HLS Compiler for Intel® Quartus® Prime Design Software provides various capabilities to enable hardware programmers to use C++ for accelerating their FPGA development process. 

What's new with the Intel HLS Compiler 18.0:

  • Continuous improvements and bug fixes to the HLS Compiler with support on the Lite, Standard, and Pro Editions of the Intel Quartus Prime design software
  • For users targeting Intel® Stratix® 10 FPGA using Intel HLS Compiler, this release provides fMAX improvements 
  • New tutorials on ac_datatypes, loop coalesce, streaming interfaces, and rand examples

The Intel® HLS Compiler for Intel Quartus® Prime design software v17.1 provides various capabilities to enable hardware programmers to use C++ for accelerating their FPGA development process.

For information about the Intel HLS Compiler, view the The Intel High Level Synthesis Compiler Release Notes.

What's new with the Intel HLS Compiler v17.1:

  • Free with Intel Quartus Prime design software v17.1
  • Supported on the Lite, Standard, and Pro Editions of the Intel Quartus Prime design software
  • Intel Stratix® 10 FPGA support
  • New QRD design example
  • Math.h library with Intel Quartus Prime design software v17.1

Optimized results:

  • Targets hard-floating point blocks on Intel FPGAs
  • Increased fMAX with pipeline insertion
  • Increased throughput with parallelism
  • Maps to device hardware resources

Accelerated development:

  • Untimed C++ to optimized RTL, which results in orders of magnitude reduction in development time
  • Fast functional debug iterations
  • Export to Platform Designer (formerly Qsys) intellectual property (IP) Library