The Intel® Advanced Link Analyzer is a state-of-the art jitter/noise eye link analysis tool that allows you to quickly and easily evaluate high-speed serial link performance. It is an ideal pre-design tool to help you understand how Intel FPGA solutions can fit your system requirements. It is also an effective tool for post-design support to assist in debug and validation.

The Intel® Advanced Link Analyzer combines the speed of a statistical link simulator with the accuracy of a time-domain waveform-based simulator to form a new hybrid behavioral simulation paradigm. With the Intel® Advanced Link Analyzer, you can quickly estimate the optimal link equalization and other electrical parameter settings for the transmitter and receiver of your system. You can also predict your link performance with high confidence.

Key Benefits and Features

The key benefits and features of the Intel® Advanced Link Analyzer are as follows:

  • Reduces time to design success
    • Silicon and package characterization/correlation of integrated models
    • Link model or simulation comprehends PVT variations
    • Hybrid simulation with statistical and time-domain analysis
    • NRZ and PAM4 modulation schemes
    • Reference clock jitter and PLL subsystem
    • Forward Error Correction (FEC)
  • Provides ease of use
    • Self-contained, holistic link analysis tool
    • Push-button link analysis to enable simulation in minutes
    • Support for industry-standard models (e.g. IBIS-AMI 6.0/6.1 and Touchstone 2.0 S-Parameter)
    • Comprehensive link performance analysis: eye diagrams, bathtub curves, jitter analysis, and waveforms
    • Fast, accurate, and comprehensive link optimization
    • Channel compliance check (including COM) and characteristics analysis
    • Comprehensive channel design environment for what-if analysis

What's New for the Intel Advanced Link Analyzer in Intel Quartus® Prime Design Software v17.1

The Intel® Advanced Link Analyzer in Intel Quartus® Prime design software has the following new features:

  • Intel Stratix® 10 and Intel Cyclone® 10 device support update - Native and/or support through IBIS-AMI models
  • IBIS-AMI Wrapper - enhanced features beyond stand-alone IBIS-AMI models
    • Joint Rx and Tx link optimization
    • Reference clock and Tx PLL modeling
  • IEEE 802.3bj/by/bs/cd RS(528,514) and RS(544, 514) FEC
  • IEEE 802.bs/cd & CEI-56G-MR-PAM4/CEI-56G-LR-PAM4 COM support

Learn More

To learn more about this tool, you can: