Design Software

Altera's broad range of development tools provide everything you need to design for Altera FPGAs, CPLDs, and SoCs.

What's New in v16.0?

  • The user-defined latency constraints work irrespective of floating-point block's presence in the primitive subsystem
  • Optimized arithmetic logic unit (ALU) folder with better QoR for MAX® 10 FPGA targets

What is DSP Builder?

DSP Builder is a digital signal processing (DSP) design tool that allows push-button HDL generation of DSP algorithms directly from MathWorks Simulink environment.

DSP Builder allows you to design algorithm, set desired data rate, clock frequency, and device offering accurate bit and cycle simulation, synthesizing fixed- and floating-point optimized HDL, auto-verify in ModelSim®- Altera software, and auto-verify/co-simulate on hardware. This tool adds additional Altera® libraries alongside existing Simulink libraries with the Altera DSP Builder Advanced Blockset and DSP Builder Standard Blockset. Altera recommends using DSP Builder Advanced Blockset for new designs. DSP Builder Standard Blockset is not recommended for new designs except as wrapper for Advanced Blockset. 

Features:

  • Go from high-level schematic into low-level optimized VHDL targeted for your Altera FPGAs, including the latest 20 nm FPGA offering
  • Perform high-performance fixed- and floating-point DSP with vector processing, such as complex IEEE 754 single-precision floating point.
  • Push-button migration of design to Altera's hard floating-point DSP block in Arria® 10 and Stratix® 10 FPGA
  • ALU folding to build custom ALU processor architectures from a flat data-rate design
  • High-level synthesis optimizations, auto-pipeline insertion and balancing, and targeted hardware mapping
  • Flexible ‘white-box’ fast Fourier transform (FFT) toolkit with open hierarchy of libraries and blocks for users to build custom FFTs
  • Use a designer-specified system clock constraint to automatically pipeline, time-division multiplex/fold, and close timing
  • Access advanced math.h functions and multichannel data
  • Generate resource utilization tables for all designs without a Quartus® Prime software compile
  • Automatically generate projects or scripts for the Quartus Prime software, TimeQuest, Qsys, and ModelSim-Altera software

MathWorks Tools Required for DSP Builder 

(sold separately here)

  • MATLAB (required)
  • Simulink (required)
  • Fixed-Point Designer (required)

Figure 1. DSP Builder Tool Flow


Figure 2. DSP Builder Advanced Blockset

Figure 2. DSP Builder Advanced Blockset

Design Examples Included:

  • Interpolating/decimating cascaded integrator comb (CIC), finite impulse response (FIR), and multichannel infinite impulse response (IIR) filters
  • 1K-, 4K-, and 8K-point FFT and inverse FFT (IFFT)
  • Cholesky or QR-based matrix solvers
  • Digital up/down conversion
  • Complex mixer
  • Beamforming
  • Black-Scholes algorithm
  • Field-oriented motor control (FOC)
  • Mandlebrot set

Table 1. DSP Builder Floating-Point QoR

High-performance floating-point FFTs  (Arria 10 device ) 

FFT Size

fMAX

[MHz]

Throughput kFFT/s

Logic

(LEs)

DSP

Blocks

M20Ks GFLOPS
Streaming FFT

4,096

477

116

3,412

48

43

28.5

4-way Parallel FFT (1.7 Giga-sample per second)

32,768

426

52

11,576

240

296

136

32-way Parallel FFT (10 Giga-sample per second in mid size Arria 10 device)

32,768

334

326

84,298

1,364

380

854

32-way Parallel FFT (64K points in mid size Arria 10 device)   

65,536

300

146

166,732

1,552

711

768