Design Software

Altera's broad range of development tools provide everything you need to design for Altera FPGAs, CPLDs, and SoCs.

DSP Builder

What is DSP Builder?

DSP Builder, consisting of an advanced and standard blockset, allows for high-performance push-button HDL generation of digital signal processing (DSP) algorithms directly from the Simulink environment. Altera recommends using the advanced blockset for new designs as it allows you to:

  • Go from high-level schematic into low-level optimized VHDL targeted for your Altera® FPGAs, including the latest 20 nm FPGA offering
  • Perform high-performance fixed- and floating-point DSP with vector processing, such as complex IEEE 754 single-precision floating point.
  • Push-button migration of design to Altera's hard floating-point DSP block in Arria® 10 and Stratix® 10 FPGA
  • Use a designer-specified system clock constraint to automatically pipeline, time-division multiplex/fold, and close timing
  • Access advanced math.h functions and multichannel data
  • Generate resource utilization tables for all designs without a Quartus® Prime software compile
  • Automatically generate projects or scripts for the Quartus Prime software, TimeQuest, Qsys, and ModelSim®-Altera software

MathWorks Tools Required for DSP Builder Advanced Blockset

(sold separately here)

  • MATLAB (required)
  • Simulink (required)
  • Fixed-Point Designer (required)

Figure 1. DSP Builder Tool Flow

Figure 1. DSP Builder Tool Flow

Figure 2. DSP Builder Advanced Blockset

Figure 2. DSP Builder Advanced Blockset

Design Examples That Come with DSP Builder

  • Interpolating/decimating cascaded integrator comb (CIC), finite impulse response (FIR), and multichannel infinite impulse response (IIR) filters
  • 1K-, 4K-, and 8K-point fast Fourier transform (FFT) and inverse FFT (IFFT)
  • Cholesky or QR-based matrix solvers
  • Digital up/down conversion
  • Complex mixer
  • Beamforming
  • Black-Scholes algorithm
  • Field-oriented motor control (FOC)
  • Mandlebrot set

Table 1. DSP Builder Floating-Point QoR

High performance floating-point FFTs  (Arria 10®

FFT Size

Fmax

[MHz]

Throughput kFFT/s

Logic

(LEs)

DSP

Blocks

M20Ks GFLOPS
Streaming FFT

4096

477

116

3412

48

43

28.5

4-way Parallel FFT (1.7 Giga-sample per second)

32,768

426

52

11,576

240

296

136

32-way Parallel FFT (10 Giga-sample per second in mid size Arria 10®)

32,768

334

326

84,298

1364

380

854

32-way Parallel FFT (64K points in mid size Arria 10®)   

65,536

300

146

166,732

1552

711

768

Updates in DSP Builder v15.1

  • DSP Builder design interface improvements
    • New dynamic finite impulse response (FIR) filter option
    • New unified control or signals block interfaces
    • New option to generate Karatsuba complex multipliers
      • Reduces resources used in fixed point
    • Avalon® interface improvements

DSP Builder and MathWorks HDL Coder Integration

Are you currently using HDL Coder and looking to integrate a DSP Builder subsystem to unlock high-performance floating-point DSP in Altera FPGAs?
Read the Model-Based Design for Altera FPGAs Using Simulink, HDL, Coder, and Altera DSP Builder Advanced Blockset (PDF) white paper for further details

 

DSP Documents

Related DSP Links